AT25SF128A datasheet(21/64 Pages) DIALOG

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Datasheet

28-Jun-2021

DS-AT25SF128A-168

Revision I

AT25SF128A

Datasheet

128-Mbit Serial NOR Flash Memory

with Dual and Quad I/O Support

6. Fast Word Read Quad I/O Data

IO0 = (x, x, D4, D0,…)

IO1 = (x, x , D5, D1,…)

IO2 = (x, x, D6, D2,…)

IO3 = (x, x, D7, D3,…)

7. Fast Word Read Quad I/O Data:the lowest address bit must be 0.

8. Security Registers Address:

Security Register 1: A23 - A16 = 00h, A15 - A8 = 00010000b, A7 - A0 = Byte Address;

Security Register 2: A23 - A16 = 00h, A15 - A8 = 00100000b, A7 - A0 = Byte Address;

Security Register 3: A23 - A16 = 00h, A15 - A8 = 00110000b, A7 - A0 = Byte Address;

9. Dummy bits and Wraps Bits

IO0 = (x, x, x, x, x, x, w4, x)

IO1 = (x, x, x, x, x, x, w5, x)

IO2 = (x, x, x, x, x, x, w6, x)

IO3 = (x, x, x, x, x, x, x, x)

10. Address, continuous Read Mode bits, Dummy bits, Manufacture ID and Device ID

IO0 = (A20, A16, A12, A8, A4, A0, M4, M0, x, x, x, x, MID4, MID0, DID4, DID0)

IO1 = (A21, A17, A13, A9, A5, A1, M5, M1, x, x, x, x, MID5, MID1, DID5, DID1)

IO2 = (A22, A18, A14, A10, A6, A2, M6, M2, x, x, x, x, MID6, MID2, DID6, DID2)

IO3 = (A23, A19, A15, A11, A7, A3, M7, M3, x, x, x, x, MID7, MID3, DID7, DID3)

8.1 CONFIGURATION AND STATUS COMMANDS

8.1.1 Write Enable (06h)

The Write Enable command is for setting the Write Enable Latch (WEL) bit. The WEL bit must be set before every Page Program,

Sector Erase, Block Erase, Chip Erase, Write Status Register, and Erase/Program Security Registers command.

The Write Enable command sequence: CS goes low sending the Write Enable command CS goes high.

Figure 3: Write Enable Sequence Diagram

SCK

MSB

00000110

OPCODE

High-Impedance

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