AT25SF128A datasheet(48/64 Pages) DIALOG

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Datasheet

28-Jun-2021

DS-AT25SF128A-168

Revision I

AT25SF128A

Datasheet

128-Mbit Serial NOR Flash Memory

with Dual and Quad I/O Support

8.4.6 64 kbytes Block Erase (D8h)

The 64 kbytes→ Block Erase command is for erasing the all data of the chosen block. A Write Enable command must previously

have been executed to set the WEL bit. The 64 kbytes Block Erase command is entered by driving CS low, followed by the

command code, and 3-byte address on SI. Any address inside the block is a valid address for the 64 kbytes Block Erase command.

CS must be driven low for the entire duration of the sequence.

The 64 kbytes Block Erase command sequence: CS goes low sending 64 kbytes Block Erase command 3-byte address on SI

CS goes high. CS must be driven high after the eighth bit of the last address byte has been latched in; otherwise the 64 kbytes

Block Erase command is not executed. As soon as CS is driven high, the self-timed Block Erase cycle (whose duration is tBE) is

initiated.

While the Block Erase cycle is in progress, the Status Register may be read to check the value of the Write-in-Progress (WIP)

bit. The WIP bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the

cycle is completed, the WEL bit is reset. A 64 kbytes Block Erase command applied to a block which is protected by the Block

Protect (BP4, BP3, BP2, BP1, BP0) bits is not executed.

Figure 36: 64 kbytes Block Erase Sequence Diagram

SCK

MSB

410 11

812

29 30

27 28

OPCODE

ADDRESS BITS A23-A0

High-Impedance

MSB

CCCCCCCC

A A

A A AA

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