LPC47N237-MD datasheet(32/138 Pages) SMSC

32 / 138 page

3.3v I/O Controller for Port Replicators and Docking Stations

Revision 0.3 (10-26-04)

Page 32

SMSC DS – LPC47N237

DATASHEET

CPU access, even if the Serial Port records new interrupts, the current indication does not change until

access is completed. The contents of the IIR are described below.

Bit 0

This bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt

is pending. When bit 0 is a logic "0", an interrupt is pending and the contents of the IIR may be used as a

pointer to the appropriate internal service routine. When bit 0 is a logic "1", no interrupt is pending.

Bits 1 and 2

These two bits of the IIR are used to identify the highest priority interrupt pending as indicated by the

Interrupt Control Table.

Bit 3

In non-FIFO mode, this bit is a logic "0". In FIFO mode this bit is set along with bit 2 when a timeout

interrupt is pending.

Bits 4 and 5

These bits of the IIR are always logic "0".

Bits 6 and 7

These two bits are set when the FIFO CONTROL Register bit 0 equals 1.

Table 8.2 – UART Interrupt Control Table

FIFO

MODE

ONLY

INTERRUPT

IDENTIFICATION

INTERRUPT SET AND RESET FUNCTIONS

BIT 3

BIT 2 BIT 1 BIT 0

PRIORITY

LEVEL

INTERRUPT

TYPE

INTERRUPT

SOURCE

INTERRUPT

RESET

CONTROL

None

Highest

Receiver Line

Status

Overrun Error,

Parity Error,

Framing Error or

Break Interrupt

Reading the Line

Status Register

Second

Received

Data

Available

Receiver Data

Available

Read Receiver

Buffer or the FIFO

drops below the

trigger level.

Second

Character

Timeout

Indication

No Characters

Have Been

Removed From or

Input to the

RCVR FIFO

during the last 4

Char times and

there is at least 1

char in it during

this time

Reading the

Receiver Buffer

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