DP8496 datasheet(11/92 Pages) NSC

11 / 92 page

30 Register List (Continued)

TABLE 32 BCLK Frequency Range

BCLK Freq

Code

BCLK Range

CLK1

CLK0

1000 s BCLK s 1500 MHz

1500 s BCLK s 1750 MHz

1750 s BCLK s 2000 MHz

2000 s BCLK s 2500 MHz

Note

Though not in binary order this table is correct

SWS SRAM Wait State

This bit allows the user to extend SRAM wait states so that

slower SRAMs may be used

0 Normal wait states Single byte burst takes 5 cycles 4

word bursts take 12 cycles and 6 byte bursts take 17

BCLK cycles

1 Extended wait states Single byte burst is extended to 6

cycles the 4 word burst transfer is extended to 16 cy-

cles and the 6 byte burst transfer is extended to 23 cy-

cles

DFP Disable Fast Page

1 Fast Page DRAM access mode will be disabled This

way normal DRAMs can be used If SRAMs are being

used then SRAM ‘‘Fast mode’’ will also be disabled

thus SRAM transfers will occur in single byteword

bursts

0 Fast Page DRAM access mode will be enabled

DD(10) DRAM Size

If DRAM is used the DP84967 needs to know the organi-

zation eg 64k x n 256k x n etc This field controls the row

and column address so that the least significant address

bits are always on the column address This will guarantee

proper refresh timing during Buffer Memory transfers The

proper bit settings are shown in Table 33

If SRAM is used these bits are ‘‘don’t care’’

TABLE 33 Organization of DRAM

DRAM Depth

Organization of DRAM

RSZ1

RSZ0

64kxn (64kx1 64kx4)

256k x n (256k x 1 256kx4)

1Mxn (1Mx1 1Mx4)

4Mxn (4Mx1 4Mx4)

RSEL DRAMSRAM Select

The DRAMSRAM switch This bit changes the memory ac-

cess timing to control static or dynamic RAM memory This

bit must be set before any accesses are attempted to buffer

memory If DRAM is selected the proper refresh timing to

initiate CAS before RAS automatic refreshing is provided

without any further intervention through the Processor Inter-

face

DRAM

SRAM

RWID RAM Data Path Width

The value of this bit is used by the SDDC to determine

whether to provide addresses for a byte-wide memory con-

figuration or word-wide configurationwhen disk or SCSI

data accesses are made The state of this bit has no effect

on the processor address pointer which always increments

by one

Byte Mode 8-bit wide buffer memory is being used All

address pointers will increment by one

Word Mode 16-bit wide buffer memory is being used

Disk and SCSI address pointers will increment by two

Setup 2 (SUP2)

61h

76543210

BPP

BPE

SPP

SPE

SID2

SID1

SID0

The contents of this register will be invalid after assertion of

the CRST pin This register must be initialized before proper

chip operation

AI Auto Increment

The Processor Pointer will increment after each ac-

cess read or write of the Buffer Memory Data register

No incrementing will occur The Processor Pointer will

remain unchanged unless it is loaded with a new value

BPP Buffer Parity Polarity

Even parity is checked or generated at the buffer mem-

ory port if enabled by the BPE bit

Odd parity is checked or generated at the buffer memo-

ry port if enabled by the BPE bit

BPE Buffer Parity Enable

Enables the checking or generation of parity at the buff-

er memory port for various types of transfers

When Writing

Parity is generated for the data exiting at

to Buffer

the buffer port except in the case of

SCSI to Buffer transfer when the parity

is generated only if SCSI Parity is not en-

abled (SPE e 0) If SPE e 1 then the

parity accompanying SCSI Bus Data is

checked upon exiting the chip at buffer

port

When Reading Parity is checked at the port where the

from Buffer

data exits the chip except in the case of

Buffer to SCSI transfer with the SCSI

Parity

disabled

here

the

parity

checked on the incoming data at the

buffer port Also in the case of proces-

sor reads of buffer memory the parity is

checked on the incoming data at the

buffer port

Parity is not generated or checked at the buffer memory

port Parity may still be employed at the SCSI port by

using the SPE bit of this register

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