...........continued

Pin

Designator

Type

Description

24

IREF

Analog input

Reference resistor pin. Connect a 28.7 kΩ 1%

resistor to AGND.

25

TRIM

Test input

30,31

VPORT_NEG4

Analog I/O

Negative port 4 output.

33,34

VPORT_NEG5

Analog I/O

Negative port 5 output.

36,37

VPORT_NEG6

Analog I/O

Negative port 6 output.

39,40

VPORT_NEG7

Analog I/O

Negative port 7 output.

41

PGD1

Digital input

Power good input from the system power supply.

42

DGND

Power

Digital ground.

43

DVDD

Power in

Regulated 3.3 V for digital circuitry. Connect

supply source if used. A 1 µF or higher filtering

capacitor should be connected between this pin

and DGND.

44

RESET_N

Digital input

Reset input - active low (0 = reset). An external 10

kΩ pull-up resistor should be connected between

46

PGD2

Digital input

Power good input from the system power supply.

47

PGD3

Digital input

Power good input from the system power supply.

48

ADDR0

Digital input

SPI address bit 0 to set chip address.

49

ADDR1

Digital input

SPI address bit 1 to set chip address.

50

ADDR2

Digital input

SPI address bit 2 to set chip address.

51

ADDR3

Digital input

SPI address bit 3 to set chip address.

52

CS_N

Digital input

SPI bus, chip select.

53

SCK

Digital input

SPI bus, serial clock input.

54

MOSI

Digital input

SPI bus, master data out/slave in.

55

MISO

Digital output

SPI bus, master data in/slave out.

56

PGD0

Digital input

Power good input from the system power supply.

An adequate ground plane on a bottom or top layer is required for adequate thermal performance. See Designing an

IEEE 802.3af/at PoE System Based on PD39208/PD39210 for additional details.

PD39208

Pins

Datasheet

DS00003555B-page 14