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STW5095T bảng dữ liệu(PDF) 37 Page - STMicroelectronics

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STW5095T bảng dữ liệu(HTML) 37 Page - STMicroelectronics

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STw5095
4 Control Registers
37/69
4.9
Interrupt control and control interface SPI out mode
Note:
Value at IRQ pin is:
CR#
(hex)
Description
D7D6D5D4
D3
D2D1
D0
Def.
CR31 (1Fh)
interrupt Mask
VLSHEN
PUSHBEN
HSDETEN
VLSHMSK
PUSHBMSK
HSDETMSK
OVFMSK
PORMSK
0000 0000
CR32 (20h)
Interrupt Status
VLSH
PUSHB
HSDET
VLSHEV
PUSHBEV
HSDETEV
OVFEV
POREV
0000 0000
CR33 (21h)
Misc. Control
X
X
SPIOHIZ
SPIOSEL(1:0)
IRQCMOS
OVFDA
OVFAD
0000 0000
Bits
Name
Value
CR31 Description
Def.
7VLSHEN
1
0
VLSH status can be seen at IRQ output
VLSH status is masked
0
6
PUSHBEN
1
0
PUSHB status can be seen at IRQ output
PUSHB status is masked
0
5
HSDETEN
1
0
HSDET status can be seen at IRQ output
HSDET status is masked
0
4VLSHMSK
1
0
VLSH event can be seen at IRQ output
VLSH event is masked
0
3
PUSHBMSK
1
0
PUSHB event can be seen at IRQ output
PUSHB event is masked
0
2
HSDETMSK
1
0
HSDET event can be seen at IRQ output
HSDET event is masked
0
1OVFMSK
1
0
OVF event can be seen at IRQ output
OVF event is masked
0
0PORMSK
1
0
POR event can be seen at IRQ output
POR event is masked
0
IRQ
(1 or Z) when (CR31 & CR32) = 00 hex
0
when (CR31 & CR32)
00 hex
≠
⎩
⎨
⎧
=



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