PIMXRT516SCVM5A datasheet(100/128 Pages) NXP

100 / 128 page

i.MX RT1170 Crossover Processors Data Sheet for Consumer Products, Rev. 1, 05/2021

100

NXP Semiconductors

Electrical characteristics

Figure 51. RGMII receive signal timing diagram with internal delay

4.9.4.4

Ethernet Quality-of-Service (QOS) electrical specifications

The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive

at timing specs/constraints for the physical interface.

It also supports the following Time Sensitive Networking (TSN) features:

•

802.1Qbv Enhancements to Scheduling Traffic

•

802.1Qbu Frame preemption

•

Time based Scheduling

Please refer to RGMII, RMII, and MII specifications in Section 4.9.4, Ethernet controller (ENET) AC

electrical specifications

4.9.5

Controller Area Network (CAN) AC electrical specifications

The Controller Area Network (CAN) module is a communication controller implementing the CAN

protocol according to the CAN with Flexible Data rate (CAN FD) protocol and the CAN 2.0B protocol

specification. The processor has three CAN modules available. Tx and Rx ports are multiplexed with other

I/O pins. See the IOMUXC chapter of the device reference manual to see which pins expose Tx and Rx

pins; these ports are named CAN_TX and CAN_RX, respectively.

Please refer to Section 4.3.2.1, General purpose I/O (GPIO) AC parameters.

4.9.6

LPUART electrical specifications

Please refer to Section 4.3.2.1, General purpose I/O (GPIO) AC parameters.

4.9.7

USB PHY parameters

This section describes the USB-OTG PHY parameters.

The USB PHY meets the electrical compliance requirements defined in the Universal Serial Bus Revision

2.0 OTG with the following amendments.

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