SC3200 datasheet(138/447 Pages) AMD

138 / 447 page

138

AMD Geode™ SC3200 Processor Data Book

SuperI/O Module

Revision 5.1

5.7.3

Acknowledge (ACK) Cycle

The ACK cycle consists of two signals: the ACK clock pulse

sent by the master with each byte transferred, and the ACK

signal sent by the receiving device (see Figure 5-15).

The master generates the ACK clock pulse on the ninth

clock pulse of the byte transfer. The transmitter releases

the ABD line (permits it to go high) to allow the receiver to

send the ACK signal. The receiver must pull down the ABD

line during the ACK clock pulse, signalling that it has cor-

rectly received the last data byte and is ready to receive the

next byte. Figure 5-16 illustrates the ACK cycle.

Figure 5-15. ACCESS.bus Data Transaction

Figure 5-16. ACCESS.bus Acknowledge Cycle

Start

Condition

Stop

Condition

ABD

ABC

MSB

ACK

12 3 - 6

23 - 8

Acknowledge

Signal From Receiver

Byte Complete

Interrupt Within

Receiver

Clock Line Held

Low by Receiver

While Interrupt

is Serviced

Start

Condition

ABC

12 3 - 6

Transmitter Stays Off Bus

During Acknowledge Clock

Acknowledge

Signal From Receiver

Data Output

by Transmitter

Data Output

by Receiver

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