SC3200 datasheet(119/447 Pages) AMD

119 / 447 page

AMD Geode™ SC3200 Processor Data Book

119

SuperI/O Module

Revision 5.1

5.4.2.5

LDN 05h and 06h - ACCESS.bus Ports 1 and 2

ACCESS.bus ports 1 and 2 (ACB1 and ACB2) are identi-

cal. Each ACB is a two-wire synchronous serial interface

compatible with the ACCESS.bus physical layer. ACB1 and

ACB2 use a 24 MHz internal clock. Six runtime registers for

each

ACCESS.bus

are

described

Section

5.7

"ACCESS.bus Interface" on page 137.

ACB1 is designated as LDN 05h and ACB2 as LDN 06h.

Table 5-13 lists the configuration registers which affect the

ACCESS.bus ports. Only the last register (F0h) is

described here (Table 5-14). See Table 5-3 "Standard

Configuration Registers" on page 111 for descriptions of

the others.

Table 5-13. Relevant ACB1 and ACB2 Registers

Index

Type

Configuration Register or Action

Reset

Value

30h

R/W

Activate. See also bit 0 of the SIOCF1 register

00h

60h

R/W

Base Address MSB register.

00h

61h

R/W

Base Address LSB register. Bits [2:0] (for A[2:0]) are RO, 000b.

00h

70h

R/W

Interrupt Number.

00h

71h

R/W

Interrupt Type. Bit 1 is R/W. Other bits are RO.

03h

74h

Report no DMA assignment.

04h

75h

Report no DMA assignment.

04h

F0h

R/W

ACB1 and ACB2 Configuration register.

00h

Table 5-14. ACB1 and ACB2 Configuration Register

Bit

Description

Index F0h

ACB1 and ACB2 Configuration Register (R/W)

This register is reset by hardware to 00h.

7:3

Reserved.

Internal Pull-Up Enable.

0: No internal pull-up resistors on AB1C/AB2C and AB1D/AB2D. (Default)

1: Internal pull-up resistors on AB1C/AB2C and AB1D/AB2D.

1:0

Reserved.

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