SC3200 datasheet(101/447 Pages) AMD

101 / 447 page

AMD Geode™ SC3200 Processor Data Book

101

General Configuration Block

Revision 5.1

4.5.2

GX1 Module Core Clock

The core clock is generated by an Analog Delay Loop

(ADL) clock generator from the internal Fast-PCI clock. The

clock can be any whole-number multiple of the input clock

between 4 and 10. Possible values are listed in Table 4-6.

At power-on reset, the core clock multiplier value is set

according to the value of four strapped balls - CLKSEL[3:0]

(EBGA balls AL13, AK3, B27, F3 / TEPBGA balls P30,

D29, AF3, B8). These balls also select the clock which is

used as input to the multiplier, as shown in Table 4-7.

4.5.3

Internal Fast-PCI Clock

The internal Fast-PCI clock can be configured to 33, 48, or

66 MHz via strap options on the CLKSEL1 and CLKSEL0

balls. These can be read in the internal Fast-PCI Clock

field in the CCFC register (GCB+I/O Offset 1Eh[9:8]). (See

Table 4-8 on page 103 details on the CCFC register.)

Note:

Not all speeds are supported. For information on supported speeds, see Section A.1 "Order Information" on page

443.

Table 4-6. Core Clock Frequency

ADL

Multiplier

Value

Internal Fast-PCI Clock Freq. (MHz)

33.33

66.67

133.3

192

266.7

166.7

240

---

200

288

---

233.3

---

266.7

---

Table 4-7. Strapped Core Clock Frequency

CLKSEL[3:0]

Straps

Internal Fast-PCI Clock

Freq. (MHz)

(GCB+I/O Offset 1Eh[9:8])

Default ADL Multiplier

Maximum Core

Clock Freq. (MHz)

Multiply By

Multiplier Value

(GCB+I/O Offset 1Eh[3:0])

0111

33.33

0100

133

1011

0101

167

1111

0110

200

0000

0111

233

0100

1000

266

1000

1001

Reserved

1100

1010

Reserved

0001

0100

192

0101

240

1001

0110

288

1101

0111

Reserved

0110

66.67

0100

266

1010

0101

Reserved

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