SC3200 datasheet(389/447 Pages) AMD

389 / 447 page

AMD Geode™ SC3200 Processor Data Book

389

Electrical Specifications

Revision 5.1

9.3.5

PCI Bus Interface

The SC3200 is compliant with PCI Bus Rev. 2.1 specifica-

tions. Relevant information from the PCI Bus specifications

is provided below.

All parameters in Table 9-17 are not 100% tested. The

parameters in this table are further described in Figure 9-

13.

Figure 9-12. Testing Setup for Slew Rate and Minimum Timing

Table 9-17. PCI AC Specifications

Symbol

Parameter

Min

Max

Unit

Comments

IOH(AC)

(Note 1)

Switching current high

-12VIO

0 < VOUT ≤ 0.3VIO,

-17.1(VIO-VOUT)mA

0.3VIO < VOUT < 0.9VIO

Equation A

(Figure 9-13)

0.7VIO < VOUT < VIO

Test point (Note 2)

-32VIO

VOUT = 0.7VIO

IOL(AC)

(Note 1)

Switching current low

16VIO

VIO > VOUT ≥ 0.6VIO

26.7VOUT

0.6VIO > VOUT > 0.1VIO

Equation B

(Figure 9-13)

0.18VIO>VOUT>0

Test point (Note 2)

38VIO

VOUT = 0.18VIO

ICL

Low clamp current

-25+(VIN+1)/0.015

-3 < VIN < -1

ICH

High clamp current

25+(VIN-VIO-1)/0.015

VIO+4 > VIN > VIO+1

SLEWR

(Note 3)

Output rise slew rate

V/ns

0.2VIO - 0.6VIO Load

SLEWF

Output fall slew rate

V/ns

0.6VIO - 0.2VIO Load

Note 1. Refer to the V/I curves in Figure 9-13. This specification does not apply to PCICLK0, PCICLK1, and PCIRST#

which are system outputs.

Note 2. Maximum current requirements are met when drivers pull beyond the first step voltage. Equations which define

these maximum values (A and B) are provided with relevant diagrams in Figure 9-13. These maximum values are

guaranteed by design.

Note 3. Rise slew rate does not apply to open-drain outputs. This parameter is interpreted as the cumulative edge rate

across the specified range, according to the test circuit in Figure 9-12.

Buffer

VCC

0.5" max.

1 K

Ω

1 K

Ω

10 pF

Output

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