SC3200 datasheet(301/447 Pages) AMD

301 / 447 page

AMD Geode™ SC3200 Processor Data Book

301

Core Logic Module - USB Controller Registers - PCIUSB

Revision 5.1

Index 06h-07h

Status Register (R/W)

Reset Value: 0280h

The PCI specification defines this register to record status information for PCI related events. This is a read/write register. However,

writes can only reset bits. A bit is reset whenever the register is written and the data in the corresponding bit location is a 1.

Detected Parity Error. This bit is set to 1 whenever the USB detects a parity error, even if the Parity Error (Response)

Detection Enable Bit (Command Register, bit 6) is disabled.

Write 1 to clear.

SERR# Status. This bit is set whenever the USB detects a PCI address error.

Write 1 to clear.

Received Master Abort Status. This bit is set when the USB, acting as a PCI master, aborts a PCI bus memory cycle.

Write 1 to clear.

Received Target Abort Status. This bit is set when a USB generated PCI cycle (USB is the PCI master) is aborted by a

PCI target.

Write 1 to clear.

Signaled Target Abort Status. This bit is set whenever the USB signals a target abort.

Write 1 to clear.

10:9

DEVSEL# Timing. (Read Only) These bits indicate the DEVSEL# timing when performing a positive decode. Since

DEVSEL# is asserted to meet the medium timing, these bits are encoded as 01b.

Data Parity Reported. (Read Only) This bit is set to 1 if the Parity Error Response bit (Command Register bit 6) is set,

and the USB detects PERR# asserted while acting as PCI master (whether or not PERR# was driven by USB).

Fast Back-to-Back Capable. The USB supports fast back-to-back transactions when the transactions are not to the same

agent.

This bit is always 1.

6:0

Reserved. Must be set to 0.

Index 08h

Device Revision ID Register (RO)

Reset Value: 08h

Index 09h-0Bh

PCI Class Code Register (RO)

Reset Value: 0C0310h

This register identifies the generic function of the USB the specific register level programming interface. The Base Class is 0Ch (Serial

Bus Controller). The Sub Class is 03h (Universal Serial Bus). The Programming Interface is 10h (OpenHCI).

Index 0Ch

Cache Line Size Register (R/W)

Reset Value: 00h

This register identifies the system cache-line size in units of 32-bit WORDs. The USB only stores the value of bit 3 in this register since

the cache-line size of 32 bytes is the only value applicable to the design. Any value other than 08h written to this register is read back

as 00h.

Index 0Dh

Latency Timer Register (R/W)

Reset Value: 00h

This register identifies the value of the latency timer in PCI clocks for PCI bus master cycles. Bits [2:0] of this register are always set to

Index 0Eh

Header Type Register (RO)

Reset Value: 00h

This register identifies the type of the predefined header in the configuration space. Since the USB is a single function device and not a

PCI-to-PCI bridge, this byte should be read as 00h.

Index 0Fh

BIST Register (RO)

Reset Value: 00h

This register identifies the control and status of Built-In Self-Test (BIST). The USB does not implement BIST, so this register is read

only.

Index 10h-13h

Base Address Register - USB_BAR0 (R/W)

Reset Value: 00000000h

31:12

Base Address. POST writes the value of the memory base address to this register.

11:4

Always 0. Indicates that a 4 KB address range is requested.

Always 0. Indicates that there is no support for prefetchable memory.

2:1

Always 0. Indicates that the base register is 32-bits wide and can be placed anywhere in 32-bit memory space.

Always 0. Indicates that the operational registers are mapped into memory space.

Table 6-41. PCIUSB: USB PCI Configuration Registers (Continued)

Bit

Description

SC3200 bảng dữ liệu(PDF) 301 Page - Advanced Micro Devices

SC3200 bảng dữ liệu(HTML) 301 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL