SH7706 datasheet(73/709 Pages) RENESAS

tên linh kiện	SH7706

Giải thích chi tiết về linh kiện	Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

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73 / 709 page

Rev. 4.00, 03/04, page 27 of 660

2.3.3

Instruction Formats

Table 2.3 explains the meaning of instruction formats and source and destination operands. The

meaning of the operands depends on the operation code. The following symbols are used.

xxxx:

Operation code

mmmm: Source register

nnnn:

Destination register

iiii:

Immediate data

dddd:

Displacement

Table 2.3

Instruction Formats

Instruction Format

Source

Operand

Destination

Operand

Instruction

Example

0format

xxxx

——

NOP

—

nnnn: register

direct

MOVT

Control register or

system register

nnnn: register

direct

STS

MACH,Rn

nformat

xxxx

nnnn

Control register or

system register

nnnn: register

indirect with pre-

decrement

STC.L

SR,@–Rn

mmmm: register

direct

Control register

or system

LDC

Rm,SR

mmmm: register

indirect with post-

increment

Control register

or system

LDC.L

@Rm+,SR

mmmm: register

indirect

—JMP

@Rm

format

xxxx

mmmm

xxxx

mmmm: PC-

relative using Rm

—BRAF

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