EDSTRG44PLCC datasheet(14/78 Pages) TI

14 / 78 page

KEY FEATURES

1–6

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key features

The TMS370 family is based on a register-to-register architecture that allows access to a register file (up to

256 bytes) in a single bus cycle. On-chip memory includes program memory (mask ROM or EPROM), static

RAM, standby RAM, and data EEPROM.

The versatile on-chip peripheral functions include an analog-to-digital converter (ADC1, ADC2, or ADC3), a

serial communications interface (SCI1 or SCI2), a serial peripheral interface (SPI), three different timer modules

(T1, T2A, and T2B), and up to 55 digital input / output (I / O) pins. The number and type of peripheral functions

(modules) is dependent on the TMS370 subfamily.

The following are key features of the TMS370 device family (not all features are available for all devices):

D Compatibility for supporting software migration between current and future microcontrollers

D CMOS EPROM technology for providing reprogrammable EPROM and one-time programmable (OTP)

program memory for prototypes and for small-volume or quick-turn production

D CMOS EEPROM technology for providing EEPROM programming with a single 5-V supply

D ADC technology for converting analog signals to digital values

D Static RAM/register file registers that offer numerous memory options

D Standby RAM that offers data protection in power-off condition

D Programmable (asynchronous and isosynchronous†) built-in serial communications interface for control of

timing, data format, and protocol

D Serial peripheral interface for providing single-mode synchronous data transmission from the CPUs to any

external peripheral devices

D Flexible operating features:

–

Power-reduction-standby and halt modes

–

Temperature options:

°C to 70°C operating temperature (L)

–40

°C to 85°C operating temperature (A)

–40

°C to 105°C operating temperature (T)

–

Input clock frequency options:

Divide-by-4 ( 0.5 MHz to 5 MHz SYSCLK ) standard oscillator

Divide-by-1 ( 2 MHz to 5 MHz SYSCLK) phase-locked loop (PLL)

–

Operating voltage range: 5 V +10%

D Flexible interrupt handling for design flexibility:

–

Two programmable interrupt levels

–

Programmable rising-edge or falling-edge detect

D System integrity features that increase flexibility during the software development phase:

–

Oscillator fault detection

–

Privileged mode lockout

–

Watchdog timer

–

Memory security (for ROM)

† Isosynchronous = isochronous

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