EMC1702 datasheet(42/60 Pages) MICROCHIP

42 / 60 page

EMC1702

DS20006455A



2020 Microchip Technology Inc.

APPLICATION NOTE: When measuring a 65nm Intel CPUs, the Ideality Setting should be the default 12h. When

measuring 45nm Intel CPUs, the Ideality Setting should be 15h.

5.15 High Limit Status Register

The High Limit Status Register contains the status bits that are set when a temperature or voltage

channel high limit is met or exceeded. If any of these bits are set, the HIGH status bit in the Status

been removed. Reading from the register will also clear the HIGH status bit in the Status Register if

the error condition has been removed.

If not masked, the ALERT pin will be set if the programmed number of consecutive alert counts have

been met and any of these status bits are set. Once set, the status bits will remain set until read unless

the ALERT pin is configured as a comparator output (see Section 4.4.2).

Bit 7 - VSENSE_HIGH - This bit is set when the VSENSE value meets or exceeds its programmed high

limit.

Bit 6 - VSRC_HIGH - This bit is set when the VSOURCE value meets or exceeds its programmed high

limit.

Bit 1 - E1HIGH - This bit is set when the External Diode 1 channel meets or exceeds its programmed

high limit.

Bit 0 - IHIGH - This bit is set when the Internal Diode channel meets or exceeds its programmed high

limit.

Table 5.18 Ideality Factor Look-Up Table (Diode Model)

SETTING

FACTOR

10h

1.0053

11h

1.0066

12h

1.0080

13h

1.0093

14h

1.0106

15h

1.0119

16h

1.0133

17h

1.0146

Table 5.19 High Limit Status Register

ADDR

R/W

DEFAULT

35h

R-C

High Limit

Status

VSENSE_

HIGH

VSRC_

HIGH

00h

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