MPC755EC datasheet(36/56 Pages) NXP

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MPC755 RISC Microprocessor Hardware Specifications, Rev. 8

Freescale Semiconductor

System Design Information

This section provides electrical and thermal design recommendations for successful application of the

MPC755.

8.1

PLL Configuration

The MPC755 PLL is configured by the PLL_CFG[0:3] signals. For a given SYSCLK (bus) frequency, the

PLL configuration signals set the internal CPU and VCO frequency of operation. These must be chosen

such that they comply with Table 8. Table 16 shows the valid configurations of these signals and an

example illustrating the core and VCO frequencies resulting from various PLL configurations and

example bus frequencies. In this example, shaded cells represent settings that, for a given SYSCLK

frequency, result in core and/or VCO frequencies that do not comply with the 400-MHz column in Table 8.

Table 16. MPC755 Microprocessor PLL Configuration Example for 400 MHz Parts

PLL_CFG

[0:3]

Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)

Bus-to-

Core

Multiplier

Core-to-

VCO

Multiplier

Bus

33 MHz

Bus

50 MHz

Bus

66 MHz

Bus

75 MHz

Bus

80 MHz

Bus

100 MHz

0100

—

200

(400)

1000

—

—200

(400)

225

(450)

240

(480)

300

(600)

1110

3.5x

—

—233

(466)

263

(525)

280

(560)

350

(700)

1010

—200

(400)

266

(533)

300

(600)

320

(640)

400

(800)

0111

4.5x

—225

(450)

300

(600)

338

(675)

360

(720)

—

1011

—250

(500)

333

(666)

375

(750)

400

(800)

—

1001

5.5x

—275

(550)

366

(733)

—

1101

200

(400)

300

(600)

400

(800)

—

0101

6.5x

216

(433)

325

(650)

—

0010

233

(466)

350

(700)

—

0001

7.5x

250

(500)

375

(750)

—

1100

266

(533)

400

(800)

—

0110

10x

333

(666)

—

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