MPC755 RISC Microprocessor Hardware Specifications Addendum for the XPC7n5BxxnnnLD Series, Rev. 2.1

4

Freescale Semiconductor

General Parameters

4.2.2

Processor Bus AC Specifications

All part numbers described herein have slower AC timing characteristics than later revisions of the part.

The affected processor bus AC timing specifications are given in Table 10.

4.2.4

L2 Bus AC Specifications

The AC timing characteristics of the L2 bus interface in 3.3 V mode are slower for parts affected by this

specification than for later revisions of the part. Additionally, the AC timing of the L2 interface is not

guaranteed in 1.8 V/2.0 V mode. These affect the following part numbers only:

•

XPC755BRX300LD

•

XPC755BRX350LD

•

XPC755BRX400LD

•

XPC755BPX300LD

•

XPC755BPX350LD

•

XPC755BPX400LD

SYSCLK input high voltage

1.8/2.0

1.5

V

3.3

2.4

V

SYSCLK input low voltage

1.8/2.0

–0.3

0.2

V

3.3

–0.3

0.4

V

1.8/2.0

—

V

3.3

2.4

—

V

1.8/2.0

—0.45

V

3.3

—0.4

V

Notes:

1. Nominal voltages; see Table 3 for recommended operating conditions.

3. Excludes test signals (LSSD_MODE, L1_TSTCLK, L2_TSTCLK) and IEEE 1149.1 boundary scan (JTAG) signals.

Table 10. Processor Bus AC Timing Specifications

At recommended operating conditions (see Table 3)

Parameter

Symbol

300, 350, 400 MHz

Unit

Min

Max

Input Hold Times: All Inputs

0.6

—

ns

Valid Times: All Outputs

—4.5

ns

Table 6. DC Electrical Specifications (continued)

Characteristic

Nominal

Bus

Symbol

Min

Max

Unit

Notes