PCMD3140IRTER datasheet(48/106 Pages) TI

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Each GPOx or GPIOx pin can be independently set for the desired drive configurations setting using the

GPOx_DRV[3:0] or GPIO1_DRV[3:0] register bits. Table 7-42 lists the drive configuration settings.

Table 7-42. GPIO or GPOx Pins Drive Configuration Settings

P0_R33_D[3:0] : GPIO1_DRV[3:0]

GPIO OUTPUT DRIVE CONFIGURATION SETTINGS FOR GPIO1

000

The GPIO1 pin is set to high impedance (floated)

001

The GPIO1 pin is set to be driven active low or active high

010 (default)

The GPIO1 pin is set to be driven active low or weak high (on-chip pullup)

011

The GPIO1 pin is set to be driven active low or Hi-Z (floated)

100

The GPIO1 pin is set to be driven weak low (on-chip pulldown) or active high

101

The GPIO1 pin is set to be driven Hi-Z (floated) or active high

110 and 111

Reserved (do not use these settings)

Similarly, the GPO1 pin can be configured using the GPO1_DRV (P0_R34) register bits.

When configured as a general-purpose output (GPO), the GPIO1 or GPOx pin values can be driven by writing

the GPIO_VAL or GPOx_VAL (P0_R41) registers. The GPIO_MON (P0_R42) register can be used to readback

the status of the GPIO1 pin when configured as a general-purpose input (GPI). Similarly, the GPI_MON

(P0_R47) register can be used to readback the status of the GPIx pins when configured as a general-purpose

input (GPI).

PCMD3140

SBASA64A – DECEMBER 2020 – REVISED JUNE 2021

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PCMD3140IRTER bảng dữ liệu(PDF) 48 Page - Texas Instruments