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MCP3461RT-E/ST bảng dữ liệu(PDF) 90 Page - Microchip Technology |
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MCP3461RT-E/ST bảng dữ liệu(HTML) 90 Page - Microchip Technology |
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90 / 118 page  MCP3461/2/4R DS20006404C-page 90 2020-2021 Microchip Technology Inc. 8.1 ADCDATA REGISTER Name Bits Address Cof ADCDATA 4/16/32 0x0 R REGISTER 8-1: ADCDATA: ADC CHANNEL DATA OUTPUT REGISTER R-0 ADCDATA[15:0] bit 15 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 ADCDATA[15:0]: ADC Output Code The data are post-calibration if the EN_OFFCAL or EN_GAINCAL bits are enabled. The data can be formatted in 16/32-bit modes depending on the DATA_FORMAT[1:0] bits setting (see Section 5.6 “ADC Output Data Format”). The ADC Channel Data Output registers always contain the most recent A/D conversion data. The register is updated at each data ready internal signal (it depends on the OSR and CONV_MODE settings). The register is latched at the start of each SPI Read command. The register is double buffered to avoid data loss. There is a small time delay, tDODR, after each data ready, where the user has to wait for the data to be available. Otherwise, data corruption can occur (when the internal data are refreshed). When IRQ_MODE[1:0] = 1x, this register becomes a 4-bit wide register containing the MDAT output codes, which are the outputs of the modulator that are represented by four comparator outputs (COMP[3:0], see Section 5.4.2 “Modulator Output Block”). |
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