NAND01GR3B datasheet(18/64 Pages) STMICROELECTRONICS

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Signal descriptions

NAND01G-B, NAND02G-B

18/64

3.7

Power-Up Read Enable, Lock/Unlock Enable (PRL)

The Power-Up Read Enable, Lock/Unlock Enable input, PRL, is used to enable and disable

the lock mechanism. When PRL is High, VIH, the device is in Block Lock mode.

If the Power-Up Read Enable, Lock/Unlock Enable input is not required, the PRL pin should

be left unconnected (Not Connected) or connected to VSS.

3.8

Write Enable (W)

The Write Enable input, W, controls writing to the Command Interface, Input Address and

Data latches. Both addresses and data are latched on the rising edge of Write Enable.

During power-up and power-down a recovery time of 10µs (min) is required before the

Command Interface is ready to accept a command. It is recommended to keep Write Enable

high during the recovery time.

3.9

Write Protect (WP)

The Write Protect pin is an input that gives a hardware protection against unwanted program

or erase operations. When Write Protect is Low, VIL, the device does not accept any

program or erase operations.

It is recommended to keep the Write Protect pin Low, VIL, during power-up and power-down.

3.10

Ready/Busy (RB)

The Ready/Busy output, RB, is an open-drain output that can be used to identify if the P/E/R

Controller is currently active. When Ready/Busy is Low, VOL, a read, program or erase

operation is in progress. When the operation completes Ready/Busy goes High, VOH.

The use of an open-drain output allows the Ready/Busy pins from several memories to be

connected to a single pull-up resistor. A Low will then indicate that one, or more, of the

memories is busy.

Refer to the Section 11.1: Ready/Busy Signal electrical characteristics for details on how to

calculate the value of the pull-up resistor.

3.11

VDD Supply Voltage

VDD provides the power supply to the internal core of the memory device. It is the main

power supply for all operations (read, program and erase).

An internal voltage detector disables all functions whenever VDD is below VLKO (see

Table 22 and Table 23) or 1.5V (for 1.8V devices) to protect the device from any involuntary

program/erase during power-transitions.

Each device in a system should have VDD decoupled with a 0.1µF capacitor. The PCB track

widths should be sufficient to carry the required program and erase currents.

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