FBSGAM02PR50 datasheet(17/33 Pages) EPC-CO

tên linh kiện	FBSGAM02PR50

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FBS-GAM02-P-R50 Datasheet

Interfacing the FBS-GAM02 to Legacy Rad-Hard PWM Controllers (continued)

b.) Zener diode voltage clamp with ASIC/FPGA Two-Phase PWM Generator.

The same Zener diode clamping circuit as shown in Figure 14 may be used to clamp the output of the UC1823A to a lower voltage level

in order to present it to an ASIC/FPGA in order to generate the requisite two-phase clock signals for the BIN and TIN logic inputs of the

FBS-GAM02-P-R50. A typical circuit for this circuit implementation is shown in Figure 15:

In the circuit of Figure 15 all the high-speed and high accuracy analog functions associated with the PWM controller are performed off-

chip from the FPGA/ASIC. The programmable logic of the FPGA/ASIC and the associated firmware code is responsible for generating

the two-phase clock with dead times required by the BIN and TIN inputs of the FBS-GAM02-P-R50.

Figure 15. Zener Diode Logic Input Voltage Clamp Circuit with

ASIC/FPGA Two-Phase Clock (With Dead Time) Generator

+12 VDC

PGND

UC1823A-SP

FPGA/

ASIC

OUT

GP01

GP02

GPI

BIN

TIN

FBSGAM02PR50 bảng dữ liệu(PDF) 17 Page - Efficient Power Conversion Corporation.