MCP48FVB21 datasheet(17/84 Pages) MICROCHIP

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DS20005466A-page 17

MCP48FVBXX

DC Notes:

This parameter is ensured by design.

This parameter is ensured by characterization.

POR/BOR voltage trip point is not slope dependent. Hysteresis implemented with time delay.

Supply current is independent of current through the resistor ladder in mode VRxB:VRxA = ‘10’.

The PDxB:PDxA = ‘01’, ‘10’, and ‘11’ configurations should have the same current.

By design, this is the worst-case current mode.

Resistance is defined as the resistance between the VREF pin (mode VRxB:VRxA = ‘10’) to VSS pin. For

dual-channel devices (MCP48FVBX2), this is the effective resistance of the each resistor ladder. The resistance

measurement is that of the two resistor ladders measured in parallel.

This gain error does not include offset error.

Within 1/2 LSb of final value when code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in 12-bit device).

10. Code range dependent on resolution: 8-bit, codes 6 to 250; 10-bit, codes 25 to 1000; 12-bit, codes 100 to 4000.

11. Variation of one output voltage to mean output voltage.

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