MCP37D31-80ESLASHTE datasheet(68/141 Pages) MICROCHIP

68 / 141 page

 2020 Microchip Technology Inc.

DS20006382A-page 68

MCP37D31-80 AND MCP37D21-80

4.11

Output Data format

The device can output the ADC data in offset binary or

two’s complement. The data format is selected by the

DATA_FORMAT bit in Address 0x62 (Register 5-20).

Table 4-19 shows the relationship between the analog

input voltage, the digital data output bits and the

overrange bit. By default, the output data format is

two’s complement.

4.12

Digital Output

The device can operate in one of the following three

digital output modes:

• Full-Rate CMOS

• Double-Data-Rate (DDR) LVDS

• Serialized DDR LVDS: Available in octal-channel

with 16-bit mode only)

The outputs are powered by DVDD18 and GND. The

digital

output

mode

selected

the

OUTPUT_MODE<1:0>

bits

Address

0x62

(Register 5-20). Figures 2-1 – 2-6 show the timing

diagrams of the digital output.

4.12.1

FULL RATE CMOS MODE

In full-rate CMOS mode, the data outputs (Q15 to Q0,

DM1 and DM2), overrange indicator (OVR), word

clock (WCK) and the data output clock (DCLK+,

DCLK–) have CMOS output levels. The digital output

should drive minimal capacitive loads. If the load

capacitance is larger than 10 pF, a digital buffer should

be used.

4.12.2

DOUBLE DATA RATE LVDS MODE

In double-data-rate LVDS mode, the output is a

parallel data stream which changes on each edge of

the output clock. See Figure 2-2 for details.

• Even-bit first option: Available for all resolution

options including 18-bit option. See Figure 2-2 for

details.

• MSb-first option: Available for the 16-bit option

only. See Figure 2-3 for details.

In multi-channel configuration, the data is output

sequentially with the WCK that is synchronized to the

first sampled channel.

The device outputs the following LVDS output pairs:

• Output Data:

- 16-/18-bit mode: Q7+/Q7- through Q0+/Q0-

- DM+/DM- (18-bit mode only)

- 14-bit mode: Q6+/Q6- through Q0+/Q0-

•OVR/WCK

• DCLK+/DCLK-

A 100Ω differential termination resistor is required for

each LVDS output pin pair. See <LVDS_LOAD> bit

option in Register 0x63 for using internal terminator.

The termination resistor should be located as close as

possible to the LVDS receiver. By default, the outputs

are standard LVDS levels: 3.5 mA output current with

a 1.15V output Common-mode voltage on a 100

 dif-

ferential load. See Address 0x63 (Register 5-21) for

more details of the LVDS mode control.

TABLE 4-19:

ADC OUTPUT CODE VS. INPUT VOLTAGE (16-BIT MODE)

Input Range

Offset Binary(1)

Two’s Complement(1)

Overrange (OVR)

AIN > AFS

1111-1111-1111-1111

0111-1111-1111-1111

AIN = AFS

1111-1111-1111-1111

0111-1111-1111-1111

AIN = AFS – 1 LSb

1111-1111-1111-1110

0111-1111-1111-1110

AIN = AFS – 2 LSb

1111-1111-1111-1100

0111-1111-1111-1100

•

AIN = AFS/2

1100-0000-0000-0000

0100-0000-0000-0000

AIN = 0

1000-0000-0000-0000

0000-0000-0000-0000

AIN = -AFS/2

0011-1111-1111-1111

1011-1111-1111-1111

•

AIN = -AFS + 2 LSb

0000-0000-0000-0010

1000-0000-0000-0010

AIN = -AFS + 1 LSb

0000-0000-0000-0001

1000-0000-0000-0001

AIN = -AFS

0000-0000-0000-0000

1000-0000-0000-0000

AIN < -AFS

0000-0000-0000-0000

1000-0000-0000-0000

Note 1:

MSb is sign bit

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