MCP37D31-80ESLASHTE datasheet(53/141 Pages) MICROCHIP

53 / 141 page

MCP37D31-80 AND MCP37D21-80

DS20006382A-page 53

 2020 Microchip Technology Inc.

4.8.2

DECIMATION FILTERS

The decimation feature is available in single and dual-

channel modes and CW octal-channel mode.

Figure 4-15 shows a simplified decimation filter block,

and Table 4-13 shows the register settings. The

decimation rate is controlled by FIR_A<8:0> and

FIR_B<7:0> register settings (Addresses 0x7A –

0x7C:

Registers 5-34 - ).

These

registers

are

thermometer encoded.

In single-channel mode, FIR B is disabled and only

FIR A is used. In this mode, the maximum

programmable decimation rate is 512x using nine

cascaded decimation stages.

In dual-channel mode or when using the Digital Down-

Conversion (DDC) in I/Q mode, both FIR A and FIR B

are used (see Figure 4-15). In this case, both channels

are set to the same decimation rate. Note that stage

1A in FIR A is unused: the user must clear FIR_A<0>

in Address 0x7A (Registers 5-34). In dual-channel

mode, the maximum programmable decimation rate is

up to 256x, which is half the single-channel decimation

rate (512x).

The overall SNR performance can be improved with

higher decimation rate. In theory, 3 dB improvement is

expected with each successive stage of decimation

(2x per stage), but the actual improvement is

approximately 2.5 dB per stage due to finite

attenuation in the FIR filters.

When using a high decimation rate option (128x or

above) in 16-bit mode, the user may consider enabling

two additional LSb output bits using the DM1DM2 bit

setting in Address 0x68 (Register 5-26). This results in

18-bit resolution. The recommended decimation rates

for adding these two additional bits are 128x or above.

This option is available for 16-bit devices only

(MCP37D31-80).

Table 4-12 summarizes the decimation rate versus

SNR performance in 16-bit and 18-bit output modes.

The results indicate that the SNR is marginally

improved with higher decimation rates. Therefore, the

user may benefit from the 18-bit output mode when a

high decimation rate is used. When a low decimation

rate is used, there is no benefit to SNR or SFDR

performance although the 18-bit output is enabled.

Table 4-13 summarizes the related control parameters

for using decimation filters.

TABLE 4-12:

DECIMATION RATE VS. SNR

PERFORMANCE

Decimation

Rate

SNR (dBFS)

16-Bit Output

Mode

18-Bit Output

Mode(1)

74.5

76.7

79.5

82.3

16x

84.8

32x

87.1

87.4

64x

89.2

89.7

128x

91.0

91.8

256x

92.0

93.2

512x

92.3

93.5

Note 1: DM1DM2 bit is enabled.

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