MCP39F511N datasheet(26/61 Pages) MICROCHIP

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DS20005473B-page 26

MCP39F511N

5.10

Zero Crossing Detection (ZCD)

The zero crossing detection block generates a logic

pulse output on the ZCD pin that is coherent with the

zero crossing of the input AC signal present on voltage

input pin (V+). The ZCD pin can be enabled and

disabled by the corresponding bit in the System

Configuration Register. When enabled, this produces a

square wave with a frequency that is the same as the

AC signal present on the voltage input. Figure 5-6

represents the signal on the ZCD pin superimposed

with the AC signal present on the voltage input in this

mode.

FIGURE 5-6:

Zero Crossing Detection

Operation (Non-Inverted, Non-Pulse).

A second mode is available that produces a

100 µs pulse. The frequency here is twice that of the

AC signal on the voltage channel input, at each zero

crossing, as shown in Figure 5-7.

FIGURE 5-7:

Zero Crossing Detection

Operation (Non-Inverted, Pulsed).

Switching modes is done by setting the corresponding

bit in the System Configuration Register.

In addition, either the toggling of this pin, or the pulse,

can be inverted. The ZCD Inversion bit is also in the

System Configuration register.

There are two bits in the System Configuration register

that can be used to modify the zero crossing. The zero

crossing output can be inverted by setting the inversion

bit, or the zero crossing can be a 100 µs pulse at each

zero crossing by setting the pulse bit.

Note that a low-pass filter is included in the signal path

that allows the zero crossing detection circuit to filter

out

the

fundamental

frequency. An

internal

compensation circuit is then used to gain back the

phase delay introduced by the low-pass filter resulting

in a latency of less than ±200 µs.

<200 µs

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