L9026 datasheet(14/60 Pages) STMICROELECTRONICS

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6.3

Operating modes

The L9026 has 4 operative modes as per below:

•

Sleep mode

•

Idle mode

•

Active mode

•

Limp Home mode

The transition between operation modes is determined according to the following levels and states:

•

logic level at IDLE pin

•

logic level at INn pins

•

PWM_SPI.OUTn bits state

•

CFG_1.ACT bit state

•

MAP_PWM.OUTn and PWM_SEL.OUTn bits state

The Figure 6 represents the possible transitions in the state diagram. The description is valid if the digital POR

signal is de-asserted (indicated as POR_N in the register map). In case of POR = 0 transitions from Active to idle

and from Limp Home to Sleep do not guarantee switch off behavior with functional timings. A POR condition is

traced in a clear on read register in the STA_1.POR bit. The behavior of the device as well as some parameters

may change depending on the operating mode of the device. Furthermore, due to the under voltage detection

circuitry which monitors VBATT and VDDIO supply voltages, some changes within the same operation mode can

be seen accordingly.

In case of VBATT < VBATT(UV_L) and IDLE = IN0 = IN1 = high device doesn't go from IDLE state to ACTIVE

state.

Starting from Active state in the condition IDLE = ’0’ and INn = ’0’ (that corresponds to the transition Active to

Sleep) to guarantee drivers turn OFF it is necessary also a SW reset.

There are different options to observe the operation mode of the device:

•

status of output channels

•

status of SPI registers

•

current consumption at VBATT pin (IVBATT)

Figure 6. State ddiagram

L9026

Operating modes

DS13397 - Rev 5

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