ADF7024BCPZ datasheet(21/24 Pages) AD

21 / 24 page

Data Sheet

ADF7024

Rev. B | Page 21 of 24

THEORY OF OPERATION

For detailed information on the operation of the ADF7024, see

the ADF7024 Hardware Reference Manual, UG-698, which is

only available as part of the ADF7024 design resource package.

SPI INTERFACE

The ADF7024 is equipped with a 4-wire SPI interface, using the

SCLK, MISO, MOSI, and CS pins. The ADF7024 always acts as

a slave to the host processor. The SPI interface allows the host

processor to perform the following operations on the ADF7024:



Read and write to the ADF7024 memory spaces.



Issue commands to the ADF7024.



Read back the status of the ADF7024.



Wake the ADF7024 from the PHY_SLEEP state.

Figure 39 shows a typical connection diagram between the

processor and the ADF7024. The diagram also shows the

direction of the signal flow for each pin.

Figure 39. Host Processor Interface

The status word of the ADF7024 is returned over the MISO

automatically each time a byte is transferred over the MOSI.

The status word contains the current ADF7024 state, the interrupt

status and flags to indicate that the ADF7024 is ready to accept a

new SPI memory access command or a radio control command.

RADIO CONTROL

The ADF7024 has five radio states designated as PHY_SLEEP,

PHY_OFF, PHY_ON, PHY_RX, and PHY_TX, as described in

Table 11. The host processor can transition the ADF7024 between

states by issuing single-byte, radio control commands over the

SPI interface.

Table 11. Radio States

State

Current

(Typical)

Conditions

PHY_SLEEP

(Deep Sleep

Mode 2)

0.18 μA

Wake-up timer off, configuration

registers not retained, entered by

issuing CMD_HW_RESET

PHY_SLEEP

(Deep Sleep

Mode 1)

0.33 μA

Wake-up timer off, configuration

registers retained

PHY_SLEEP

(WUC

enabled)

0.75 μA

Wake-up timer on using the 32 kHz

RC oscillator, configuration

registers retained

PHY_OFF

1.0 mA

PHY_ON

1.0 mA

PHY_TX

24.1 mA

10 dBm, 868 MHz

PHY_RX

12.8 mA

MEMORY MAP

The ADF7024 memory map is shown in Figure 40. Each memory

space consists of 8-bit registers with an address length of 11 bits.

Figure 40. Memory Map

Configuration Registers

The configuration registers consist of 64 bytes of memory space

used to configure the operation of the ADF7024. The radio profile

registers form part of this memory space. The configuration

registers are retained in the PHY_SLEEP radio state.

Auxiliary Registers

The auxiliary registers consist of 256 bytes of memory space

used for auxiliary radio functions or observation of the radio

blocks of the ADF7024.

Packet RAM

The packet RAM memory consists of 240 bytes of memory for

storage of data from valid received packets and packet data to

be transmitted.

Auxiliary RAM

The auxiliary RAM memory is reserved for use by the ADF7024.

RADIO BLOCKS

Frequency Synthesizer

A fully integrated RF synthesizer is used to generate both the

transmit signal and the local oscillator (LO) signal of the

receiver. A high speed, fully automatic calibration scheme

ensures that the frequency and amplitude characteristics of the

VCO are maintained over temperature, supply voltage, and process

variations. The receive and transmit synthesizer bandwidths are

automatically and independently configured to achieve optimum

phase noise and settling time.

ADF7024

HOST

PROCESSOR

SCLK

MOSI

MISO

IRQ_GP3

GPIO

SCLK

MOSI

MISO

IRQ

NOT USED

AUXILIARY RAM

16 BYTES

0x300

0x3FF

0x0FF

0x010

0x00F

0x000

AUXILIARY REGISTERS

256 BYTES

PACKET RAM

240 BYTES

0x100

0x13F

CONFIGURATION REGISTERS

64 BYTES

RETAINED IN PHY_SLEEP

NOT RETAINED IN PHY_SLEEP

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