Data Sheet

ADF7024

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 4. Pin Configuration

Table 10. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

CREGRF1

Regulator Voltage for RF. For regulator stability and noise rejection, place a 220 nF capacitor between this

pin and ground.

2

RBIAS

External Bias Resistor. Place a 36 kΩ resistor with 2% tolerance between this pin and ground.

3

CREGRF2

Regulator Voltage for RF. For regulator stability and noise rejection, place a 220 nF capacitor between this

pin and ground.

4

RFI_P

LNA Positive Input in Receive Mode.

5

RFI_N

LNA Negative Input in Receive Mode.

6

RFO

PA Output.

7

VDDBAT2

Power Supply Pin 2. Place decoupling capacitors to the ground plane as close as possible to this pin.

8

NC

No Connect. Do not connect to this pin.

9

CREGVCO

Regulator Voltage for the VCO. For regulator stability and noise rejection, place a 220 nF capacitor between

this pin and ground.

10

VCOGUARD

Guard/Screen for VCO. Connect this pin to Pin 9.

11

CREGSYNTH

Regulator Voltage for the Synthesizer. For regulator stability and noise rejection, place a 220 nF capacitor

between this pin and ground.

12

CWAKEUP

External Capacitor for Wake-Up Control. Place a 150 nF capacitor between this pin and ground.

13

XOSC26P

Crystal Oscillator, Positive. Connect the 26 MHz reference crystal between this pin and XOSC26N. If an

external reference is connected to XOSC26N, leave this pin open circuited.

14

XOSC26N

Crystal Oscillator, Negative. Connect the 26 MHz reference crystal between this pin and XOSC26P.

Alternatively, an external 26 MHz reference signal can be ac-coupled to this pin.

15

DGUARD

Internal Guard/Screen for the Digital Circuitry. Connect this pin to Pin 16, CREGDIG1.

16

CREGDIG1

Regulator Voltage for Digital Section of the Chip. For regulator stability and noise rejection, place a 220 nF

capacitor between this pin and ground.

17

GP0

Digital GPIO Pin 0.

18

GP1

Digital GPIO Pin 1.

19

GP2

Digital GPIO Pin 2.

20

IRQ_GP3

Interrupt Request/Digital GPIO Test Pin 3.

21

MISO

Serial Port Master Input/Slave Output.

22

SCLK

Serial Port Clock.

23

MOSI

Serial Port Master Output/Slave Input.

24

CS

from inadvertently waking the ADF7024 from sleep.

25

GP4

Digital GPIO Test Pin 4.

NOTES

1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.

2. CONNECT THE EXPOSED PAD TO GND.

24 CS

23 MOSI

22 SCLK

21 MISO

20 IRQ_GP3

19 GP2

18 GP1

17 GP0

1

2

3

4

5

6

7

8

CREGRF1

RBIAS

CREGRF2

RFI_P

RFI_N

RFO

VDDBAT2

NC

TOP VIEW

(Not to Scale)

ADF7024

EPAD

Rev. B | Page 13 of 24