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CDCE706 bảng dữ liệu(PDF) 23 Page - Texas Instruments

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tên linh kiện CDCE706
Giải thích chi tiết về linh kiện  PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER / MULTIPLIER / DIVIDER
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CDCE706 bảng dữ liệu(HTML) 23 Page - Texas Instruments

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3% Down Spread
2% Down Spread
fmodulation − kHz
+0.4 Center Spread
+0.25 Center Spread
Further EMI Reduction
11.3dB
7dB
Slew−Rate for Vccout = 2.5 V
11.3dB
11.3dB
7dB
7dB
Slew−Rate for Vccout = 3.3 V
nom−1
nom
nom+2
−3dB
6.4dB
nom−1
nom
nom+2
−2.5dB
5.6dB
CDCE706
SCAS815A – OCTOBER 2005 – REVISED OCTOBER 2005
Figure 15. EMI Reduction vs fModulation and fAmount
The optimum damping is a combination of modulation amount, modulation frequency and the harmonics which
are considered. Note that higher order harmonic frequencies results in stronger EMI reduction because of
respective higher frequency deviation.
As seen in Figure 16 and Figure 17, a slower output slew rate and/or smaller output signal amplitude helps to
reduce EMI emission even more. Both measures reduce the RF energy of clock harmonics. The CDCE706
allows slew rate control in four steps between 0.6 ns and 3.3 ns (Byte 19-24, Bit [5:4]). The output amplitude is
set by the two independent output supply voltage pins, VCCOUT1 and VCCOUT2, and can vary from 2.3 V to 3.6 V.
Even a lower output supply voltage down to 1.8 V works, but the maximum frequency has to be considered.
Figure 16. EMI Reduction vs Slew-Rate and Vccout
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