ADPD4100 datasheet(30/101 Pages) AD

30 / 101 page

ADPD4100/ADPD4101

Data Sheet

Rev. 0 | Page 30 of 101

Optimizing Position of Integration Sequence

It is critical that the zero crossing of the output response of the

BPF be aligned with the integration sequence such that the

positive integration is aligned with the positive portion of the

BPF output response and the negative integration is aligned with

the negative portion of the BPF output response (see Figure 35).

A simple test to find the zero crossing is to set up the circuit so

that the LED is reflecting off a reflector at a fixed distance from

the photodiode such that a steady dc level of photodiode current

is provided to the ADPD4100/ADPD4101. Monitor the output

while sweeping the integrator offset, INTEG_OFFSET_x,

Bits[12:5], from a low value to a high value in 1 μs steps. The

zero crossing is located when a relative maxima is seen at the

output. The zero crossing can then be identified with much finer

precision by sweeping the INTEG_OFFSET_x, Bits[4:0] in

31.25 ns increments. It is critical to identify the zero crossing in

such a fine precision to achieve the highest SNR performance.

The optimal timing point is a function of TIA bandwidth which

varies with TIA gain. To achieve the maximum SNR at each TIA

gain setting, it is recommended that the user find the optimal

timing point at each TIA gain setting for a given use case.

Because there is minimal device to device variation in this

optimal timing point, that same integrator offset timing for

each gain setting can be used for all devices. To use the same

integrator timing for all TIA gain settings without reoptimizing

for each TIA gain setting, 200 kΩ TIA gain optimal timing must

be used for the other TIA gain settings.

Improving SNR Using Multiple Pulses

The ADPD4100/ADPD4101 use short LED pulses, on the order

of 2 μs or 3 μs. The SNR of a single pulse is approximately 72 dB

to 76 dB, depending on the TIA gain. The SNR can be extended

to ~100 dB by increasing the number of pulses per sample and

filtering to a relevant signal bandwidth, for example, 0.5 Hz to

20 Hz for a heart rate signal. The SNR increases as the square

root of the number of pulses. Thus, for every doubling of pulses,

3 dB of SNR increase is achieved. The number of pulses is

increased with the NUM_REPEAT_x bits. The resulting data

for a particular time slot is the summation of ADC conversions

that are NUM_REPEAT_x times. If the number of bits required

for the result is larger than the number of output bits desired by

the user, the most significant bits of the accumulated values can

be selected by DARK_SHIFT_x, LIT_SHIFT_x, and

SIGNAL_SHIFT_x bits. DARK_SHIFT_x, LIT_SHIFT_x, and

SIGNAL_SHIFT_x shift the output data to the right before

writing to the FIFO. For example, an 18-bit accumulated value

can be shifted to write only the upper 16 bits to the FIFO.

Optionally, 24-bit or 32-bit output can be written to the FIFO.

PRECONDITION

LED

–

INTEGRATOR

SEQUENCE

ADC CHANNEL 1

ADC CHANNEL 2

(IF ENABLED)

START OF TIME SLOT

PRE_WIDTH_x

LED_OFFSET_x

PERIOD

(AUTOMATICALLY CALCULATED)

LED_WIDTH_x

INTEG_OFFSET_x

INTEG_WIDTH_x

ADC CONVERSION(S)

TIA OUTPUT

BPF OUTPUT

INTEGRATOR

OUTPUT

ZERO CROSSING

REPEAT NUM_REPEAT_x TIMES

Figure 35. Single Analog Integration per ADC Conversion with Continuous Connect Mode

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