TMS320AV7110 datasheet(16/131 Pages) TI

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DSP

TMS320AV7110

Revision 3.1

10/08/99 22:18

Page 16

4. ARM CPU

4.1 Features

•

Runs at 40.5 MHz

•

Supports byte (8-bit), half-word (16-bit), and word (32-bit) data types

•

Reads instructions from on-chip ROM or from the Extension Bus

•

Can switch between ARM (32-bit) or Thumb (16-bit) instruction mode

•

32-bit data and 32-bit address lines

•

7 processing modes

•

Two interrupts, FIQ and IRQ

The 32-bit ARM processor running at 40.5 MHz and its associated firmware provide the following:

•

initialization and management of all hardware modules

•

service for selected interrupts generated by hardware modules and I/O ports

•

application program interface (API) for users to develop their own applications

The on-chip SRAM (also referred to as Internal Data RAM in this document) provides the space

necessary for the ‘AV7110 to properly decode transport bit-streams without losing any packets. The

run-time support library (RTSL) and all user application software are located outside the ‘AV7110.

Details of the firmware and RTSL are provided in a separate software specification document.

The CPU in the ‘AV7110 is a 32-bit RISC processor, the ARM7TDMI/Thumb, which has the

capability to execute instructions in 16- or 32-bit format at a clock frequency of 40.5 MHz. The

regular ARM instructions are exactly one word (32-bit) long, and the data operations are only

performed on word quantities. The LOAD and STORE instructions however, can transfer either byte,

half-word or word quantities.

The Thumb uses the same 32-bit architecture with a 16-bit instruction set. That is, it retains the 32-bit

performance but reduces the code size with 16-bit instructions. With 16-bit instruction, the Thumb still

gives 70 - 80% of the performance of the ARM running ARM instructions from 32-bit memory. ARM

and Thumb are used interchangeably, throughout this document.

4.2 Block Diagram

ARM uses a LOAD and STORE architecture; i.e. all operations are on the registers. ARM has 7

different processing modes with 16, 32-bit registers visible in user mode. In the Thumb state, there are

only 8 registers available in user mode. The high registers may still be accessed through special

instructions in this case. The instruction pipeline is three stage, fetch

→ decode → execute, and most

instructions only take one cycle to execute. Figure 4 shows the data path of ARM processor core.

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