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AX88852 bảng dữ liệu(PDF) 30 Page - ASIX Electronics Corporation |
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AX88852 bảng dữ liệu(HTML) 30 Page - ASIX Electronics Corporation |
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30 / 39 page ![]() AX88850 PRELIMINARY ASIX ELECTRONICS CORPORATION 30 4.7 Partition Status Register (PARTITION) Page 0 Address 2h Bit Bit Name Access Bit Description D15-D10 Reserved undefined when read. D9-D0 PART[9: 0] RO The respective port‘s PART bit is set to “1” when Partitioning is sensed on that port. After reset, these bits are cleared to “0”. Page 1 Address 2h Bit Bit Name Access Bit Description D15-D8 Reserved undefined when read. D7-D0 PART[17: 10] RO The respective port‘s PART bit is set to “1” when Partitioning is sensed on that port. After reset, these bits are cleared to “0”. 4.8 Jabber Status Register (JABBER) Page 0 Address 3h Bit Bit Name Access Bit Description D15-D10 Reserved undefined when read. D9-D0 JAB[9: 0] RO The respective port‘s JAB bit is set to “1” when Jabber condition is detected on that port. After reset, these bits are cleared to “0”. Page 1 Address 3h Bit Bit Name Access Bit Description D15-D8 Reserved undefined when read. D7-D0 JAB[17: 10] RO The respective port‘s JAB bit is set to “1” when Jabber condition is detected on that port. After reset, these bits are cleared to “0”. 4.9 Administration Register (ADMIN) Page 0 Address 4h Bit Bit Name Access Bit Description D15-D10 Reserved Written as “0” for future compatibility concern. undefined by read. D9-D0 ADMIN[9: 0] R/W Administration Disable : Setting these bits to “0” enable the respective port (TX and RX). Writing a 1 to any bit will disable that port. After reset, these bits default to “0” ( all ports enable ). Note that port enable/disable action will occur at the next network idle period. Page 1 Address 4h Bit Bit Name Access Bit Description D15-D8 Reserved Written as “0” for future compatibility concern. undefined by read. D7-D0 ADMIN[17: 10] R/W Administration Disable : Setting these bits to “0” enable the respective port (TX and RX). Writing a 1 to any bit will disable that port. After reset, these bits default to “0” ( all ports enable ). Note that port enable/disable action will occur at the next network idle period. |
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