AX88852 datasheet(14/39 Pages) ASIX

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AX88850

PRELIMINARY

ASIX ELECTRONICS CORPORATION

2.2 MII interface ( two individual MII ports )

Signal Name

Type Pin No.

Description

TX_ER

(share)

O/ML

Transmit Error : TX_ER is transition synchronously with respect to the rising

edge of TX_CLK . Asserted high when a code violation is request to be send

TXD[3:0]

(share)

O/ML

97-94

Transmit Data : TXD[3:0] is transition synchronously with respect to the

rising edge of TX_CLK. For each TX_CLK period in which TX_EN is

asserted, TXD[3:0] are accepted for transmission by the PHY.

TX_EN[0]

TX_EN[1]

O/L

Transmit Enable : TX_EN is transition synchronously with respect to the

rising edge of TX_CLK. TX_EN indicates that the port is presenting nibbles

on TXD [3:0] for transmission.

RXD[0][3:0]

RXD[1][3:0]

I/PU

86-83

102-99

Receive Data : RXD [3:0] is driven by the PHY synchronously with respect to

RX_CLK.

RX_ER[0]

RX_ER[1]

I/PD

104

Receive Error : RX_ER ,is driven by PHY and synchronous to RX_CLK, is

asserted for one or more RX_CLK periods to indicate to the port that an error

has detected.

RX_CLK[0]

RX_CLK[1]

105

Receive Clock : RX_CLK is a continuous clock that provides the timing

reference for the transfer of the RX_DV,RXD [3:0] and RX_ER signals from

the PHY to the MII port of the repeater.

RX_DV[0]

RX_DV[1]

I/PD

106

Receive Data Valid : RX_DV is driven by the PHY synchronously with

respect to RX_CLK. Asserted high when valid data is present on RXD [3:1].

CRS[0]

CRS[1]

I/PD

107

Carrier Sense : Asynchronous signal CRS is asserted by the PHY when either

the transmit or receive medium is non-idle.

COL

(share)

O/ML

Collision Signal :This pin indicates collision(s) , that occurred at the collision

domain of the hub, to MII interface devices. Both the MII port use this signal

commonly.

OPT0

OPT1

I/PU

108

Option for external device type : Default ‘high’ is for PHY type device.

Otherwise, ‘low’ for MAC type device.

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