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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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HT83072 bảng dữ liệu(PDF) 15 Page - Holtek Semiconductor Inc |
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HT83072 bảng dữ liệu(HTML) 15 Page - Holtek Semiconductor Inc |
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15 / 21 page  HT83XXX Rev. 0.10 15 August 25, 2003 Preliminary Reset There are 3 ways in which a reset can occur: · RES reset during normal operation · RES reset during HALT · WDT time-out reset during normal operation The WDT time-out during HALT is different from other chip reset conditions, since it can perform a ²warm re - set ² that resets only the PC and SP, leaving the other cir- cuits in their original state. Some registers remain un- changed during any other reset conditions. Most registers are reset to their ²initial condition² when the re- set conditions are met. By examining the PDF flag and TO flag, the program can distinguish between different ²chip resets². TO PDF RESET Conditions 0 0 RES reset during power-up u u RES reset during normal operation 0 1 RES wake-up HALT 1 u WDT time-out during normal operation 1 1 WDT wake-up HALT Note: ²u² stands for ²unchanged² To guarantee that the system oscillator has started and stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses after a system power up or when awakening from a HALT state. When a system power up occurs, the SST delay is added during the reset period. But when the reset co- mes from the RES pin, the SST delay is disabled. Any wake-up from HALT will enable the SST delay. Reset Timing Chart Reset Circuit Reset Configuration The functional unit chip reset status are shown below. PC 000H Interrupt Disable Prescaler Clear WDT Clear. After master reset, WDT begins counting Timer counter Off Input/output ports Input mode SP Points to the top of the stack Timer Counter 0/1 The TMR0/TMR1 is internal clock source only, i.e. (TM1, TM0)=(1,0). There is a 3-bit prescaler (TMRS2, TMRS1, TMRS0) which defines different division ratio of TMR0/TMR1 ¢s clock source. Label Bits Function TMRS2, TMRS1, TMRS0 0~2 Defines the operating clock source (TMRS2, TMRS1, TMRS0) 000: clock source/2 001: clock source/4 010: clock source/8 011: clock source/16 100: clock source/32 101: clock source/64 110: clock source/128 111: clock source/256 TE 3 Defines the TMR0/TMR1 active edge of timer counter TON 4 Enable/disable timer counting (0=disabled; 1=enabled) ¾ 5 Unused bit, read as ²0² TM0, TM1 6 7 Defines the operating mode (TM1, TM0) TMR0C/TMR1C Register Note: TMR0C/TMR1C bit 3 always write ²0² TMR0C/TMR1C bit 5 always write ²0² TMR0C/TMR1C bit 6 always write ²1² TMR0C/TMR1C bit 7 always write ²0² t S S T R E S V D D S S T T i m e - o u t C h i p R e s e t R E S V D D W D T H A L T W D T T i m e - o u t R e s e t R E S C o l d R e s e W a r m R e s e t P o w e r - o n D e t e c t i n g S S T 1 0 - s t a g e R i p p l e C o u n t e r O S C I |
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