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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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HT83072 bảng dữ liệu(PDF) 8 Page - Holtek Semiconductor Inc |
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HT83072 bảng dữ liệu(HTML) 8 Page - Holtek Semiconductor Inc |
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8 / 21 page  HT83XXX Rev. 0.10 8 August 25, 2003 Preliminary Functional Description Execution Flow The system clock for the HT83XXX series is derived from RC oscillator. It is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while de- coding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruc- tion to effectively execute within one cycle. If an instruc- tion changes the program counter, two cycles are required to complete the instruction. Program Counter - PC The 11-bit program counter (PC) controls the sequence in which the instructions stored in program ROM are ex- ecuted. After accessing a program memory word to fetch an in- struction code, the contents of the program counter are incremented by one. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip ex- ecution, loading PCL register, subroutine call, initial re- set, internal interrupt or return from subroutine, the PC manipulates the program transfer by loading the ad- dress corresponding to each instruction. The conditional skip is activated by instruction. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is ob- tained. The lower byte of the program counter (PCL) is a read/write register (06H). Moving data into the PCL per- forms a short jump. The destination must be within 256 locations. When a control transfer takes place, an additional dummy cycle is required. Mode Program Counter *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 Initial Reset 00000000000 Time Base Overflow 00000000100 Timer Counter 0 Overflow 00000001000 Timer Counter 1 Overflow 00000001100 Skip PC+2 Loading PCL *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0 Jump, Call Branch #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 Return from Subroutine S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 Program Counter Note: *10~*0: Program counter bits S10~S0: Stack register bits #10~#0: Instruction code bits @7~@0: PCL bits T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 F e t c h I N S T ( P C ) E x e c u t e I N S T ( P C - 1 ) F e t c h I N S T ( P C + 1 ) E x e c u t e I N S T ( P C ) F e t c h I N S T ( P C + 2 ) E x e c u t e I N S T ( P C + 1 ) P C P C + 1 P C + 2 S y s t e m C l o c k P C Execution Flow |
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