PCI1031 datasheet(67/100 Pages) TI

67 / 100 page

PCI1031

PCI-TO-PC CARD16 CONTROLLER UNIT

SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

ExCA memory window 0–4 start-address low-byte register (index 10h, 18h, 20h, 28h, 30h)

ExCA memory window 0 start-address low byte

Offset:

CardBus socket address + 810h; Card A ExCA offset 10h

Card B ExCA offset 50h

ExCA memory window 1 start-address low byte

Offset:

CardBus socket address + 818h; Card A ExCA offset 18h

Card B ExCA offset 58h

ExCA memory window 2 start-address low byte

Offset:

CardBus socket address + 820h; Card A ExCA offset 20h

Card B ExCA offset 60h

ExCA memory window 3 start-address low byte

Offset:

CardBus socket address + 828h; Card A ExCA offset 28h

Card B ExCA offset 68h

ExCA memory window 4 start-address low byte

Offset:

CardBus socket address + 830h; Card A ExCA offset 30h

Card B ExCA offset 70h

Type:

Read/write

Default:

00h

Size:

One byte

Description: These registers contain the low byte of the memory window start address for memory

windows 0, 1, 2, 3, and 4. The eight bits of these registers correspond to bits A19–A12 of the

start address.

ExCA memory window 0–4 start-address high-byte register (index 11h, 19h, 21h, 29h, 31h)

ExCA memory window 0 start-address high byte

Offset:

CardBus socket address + 811h; Card A ExCA offset 11h

Card B ExCA offset 51h

ExCA memory window 1 start-address high byte

Offset:

CardBus socket address + 819h; Card A ExCA offset 19h

Card B ExCA offset 59h

ExCA memory window 2 start-address high byte

Offset:

CardBus socket address + 821h; Card A ExCA offset 21h

Card B ExCA offset 61h

ExCA memory window 3 start-address high byte

Offset:

CardBus socket address + 829h; Card A ExCA offset 29h

Card B ExCA offset 69h

ExCA memory window 4 start-address high byte

Offset:

CardBus socket address + 831h; Card A ExCA offset 31h

Card B ExCA offset 71h

Type:

Read/write (see individual bit descriptions)

Default:

00h

Size:

One byte

Description: These registers contain the high byte of the memory window start address for memory

windows 0, 1, 2, 3, and 4. In addition, the memory window data width and wait states are set in

this register. Refer to Table 32 for a complete description of the register contents.

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