10 Layout

10.1 Layout Guidelines

Mount the TMP144 to a PCB as shown in Figure 10-1. Obtaining acceptable performance with alternate layout

schemes is possible, however this layout produces good results and is intended as a guideline:

• Bypass the V+ pin to ground with a low-ESR ceramic bypass-capacitor. The typical recommended bypass

capacitance is a 0.1-μF ceramic capacitor with a X5R or X7R dielectric. The optimum placement is closest to

the V+ and GND pins of the device. Take care to minimize the loop area formed by the bypass-capacitor

connection, the V+ pin, and the GND pin of the IC. Alternatively, the bypass capacitor can also be grounded

through a via connected to the GND plane.

• Use larger copper area pads to reduce self-heating and lower thermal resistance to the environment.

• If possible, use PCB boards with thick copper layers.

• If possible, do not use stain to protect the IC because stain can increase thermal resistance.

10.2 Layout Example

0.1µ F

VIA to power plane

VIA to ground plane

B2/

RX

A1/

V+

B1/

TX

A2/

GND

Figure 10-1. Layout Example

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TMP144

SBOS891A – OCTOBER 2018 – REVISED FEBRUARY 2021

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