the configuration register is set to '1'. The clearing of the flag bits depends on the setting of the latch bit (LC) in

the configuration register.

Read of Configuration Register

FH Bit

(Transparent Mode)

FL Bit

(Transparent Mode)

FH Bit

(Latch Mode)

FL Bit

(Latch Mode)

Measured

Temperature

Time

Figure 7-2. Temperature Flag Functional Diagram

The LC bit in the configuration register when set to '1' is used to latch the value of the flag bits (FH and FL) until

the host issues a read command to the configuration register. The flag bits are set to '0' when a read command

is received by the device.

The LC bit when configured as '0', configures the device to operate in transparent mode, where the flag bits (FH

and FL) are cleared only when the result of the temperature conversion is within the temperature limits.

7.4.6 Interrupt Functionality

The TMP144 interrupts the host by disconnecting the bus and issuing an interrupt request by holding the bus low

if all of following conditions are met as shown in Figure 7-3.

• INT_EN in the configuration register is set to 1;

• The temperature result of the last conversion is greater than the value in the temperature high limit register or

less than the value in the temperature low limit register (also indicated by a 1 in either FH or FL, respectively);

• The bus is logic high and idle for more than 28 ms.

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TMP144

SBOS891A – OCTOBER 2018 – REVISED FEBRUARY 2021

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