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TMS320F28375DPZP bảng dữ liệu(PDF) 165 Page - Texas Instruments |
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TMS320F28375DPZP bảng dữ liệu(HTML) 165 Page - Texas Instruments |
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165 / 226 page  8.12.5.1 SPI Electrical Data and Timing Note All timing parameters for SPI High-Speed Mode assume a load capacitance of 5 pF on SPICLK, SPISIMO, and SPISOMI. For more information about the SPI in High-Speed mode, see the Serial Peripheral Interface (SPI) chapter of the TMS320F2837xD Dual-Core Microcontrollers Technical Reference Manual . To use the SPI in High-Speed mode, the application must use the high-speed enabled GPIOs (see Section 7.4.5). 8.12.5.1.1 SPI Master Mode Timings Section 8.12.5.1.1.1 lists the SPI master mode timing requirements. Section 8.12.5.1.1.2 lists the SPI master mode switching characteristics (clock phase = 0). Section 8.12.5.1.1.3 lists the SPI master mode switching characteristics (clock phase = 1). Figure 8-72 shows the SPI master mode external timing where the clock phase = 0. Figure 8-73 shows the SPI master mode external timing where the clock phase = 1. 8.12.5.1.1.1 SPI Master Mode Timing Requirements NO. (BRR + 1) CONDITION(1) MIN MAX UNIT High Speed Mode 8 tsu(SOMI)M Setup time, SPISOMI valid before SPICLK Even, Odd 1 ns 9 th(SOMI)M Hold time, SPISOMI valid after SPICLK Even, Odd 5 ns Normal Mode 8 tsu(SOMI)M Setup time, SPISOMI valid before SPICLK Even, Odd 20 ns 9 th(SOMI)M Hold time, SPISOMI valid after SPICLK Even, Odd 0 ns (1) The (BRR + 1) condition is Even when (SPIBRR + 1) is even or SPIBRR is 0 or 2. It is Odd when (SPIBRR + 1) is odd and SPIBRR is greater than 3. 8.12.5.1.1.2 SPI Master Mode Switching Characteristics (Clock Phase = 0) over recommended operating conditions (unless otherwise noted) NO. PARAMETER (BRR + 1) CONDITION(1) MIN MAX UNIT General 1 tc(SPC)M Cycle time, SPICLK Even 4tc(LSPCLK) 128tc(LSPCLK) ns Odd 5tc(LSPCLK) 127tc(LSPCLK) 2 tw(SPC1)M Pulse duration, SPICLK, first pulse Even 0.5tc(SPC)M – 1 0.5tc(SPC)M + 1 ns Odd 0.5tc(SPC)M +0.5tc(LSPCLK) – 1 0.5tc(SPC)M +0.5tc(LSPCLK) + 1 3 tw(SPC2)M Pulse duration, SPICLK, second pulse Even 0.5tc(SPC)M – 1 0.5tc(SPC)M + 1 ns Odd 0.5tc(SPC)M –0.5tc(LSPCLK) – 1 0.5tc(SPC)M –0.5tc(LSPCLK) + 1 23 td(SPC)M Delay time, SPISTE active to SPICLK Even 1.5tc(SPC)M - 3tc(SYSCLK) – 7 1.5tc(SPC)M - 3tc(SYSCLK) + 5 ns Odd 1.5tc(SPC)M - 4tc(SYSCLK) – 7 1.5tc(SPC)M - 4tc(SYSCLK) + 5 24 tv(STE)M Valid time, SPICLK to SPISTE inactive Even 0.5tc(SPC)M – 7 0.5tc(SPC)M + 5 ns Odd 0.5tc(SPC)M –0.5tc(LSPCLK) – 7 0.5tc(SPC)M –0.5tc(LSPCLK) + 5 www.ti.com TMS320F28379D, TMS320F28379D-Q1, TMS320F28378D, TMS320F28377D TMS320F28377D-Q1, TMS320F28376D, TMS320F28375D, TMS320F28374D SPRS880O – DECEMBER 2013 – REVISED FEBRUARY 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 165 Product Folder Links: TMS320F28379D TMS320F28379D-Q1 TMS320F28378D TMS320F28377D TMS320F28377D-Q1 TMS320F28376D TMS320F28375D TMS320F28374D |
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