TMS320F28375DPZP datasheet(61/226 Pages) TI

61 / 226 page

XRS

£100 nF

2.2 k

– 10 k

DDIO

Figure 8-4. Reset Circuit

8.9.2.1 Reset Sources

The following reset sources exist on this device: XRS, WDRS, NMIWDRS, SYSRS, SCCRESET, and

HIBRESET. See the Reset Signals table in the System Control chapter of the TMS320F2837xD Dual-Core

Microcontrollers Technical Reference Manual .

The parameter th(boot-mode) must account for a reset initiated from any of these sources.

CAUTION

Some reset sources are internally driven by the device. Some of these sources will drive XRS low.

Use this to disable any other devices driving the boot pins. The SCCRESET and debugger reset

sources do not drive XRS; therefore, the pins used for boot mode should not be actively driven by

other devices in the system. The boot configuration has a provision for changing the boot pins in

OTP; for more details, see the TMS320F2837xD Dual-Core Microcontrollers Technical Reference

Manual .

8.9.2.2 Reset Electrical Data and Timing

Section 8.9.2.2.1 shows the reset ( XRS) timing requirements. Section 8.9.2.2.2 shows the reset ( XRS)

switching characteristics. Figure 8-5 shows the power-on reset. Figure 8-6 shows the warm reset.

8.9.2.2.1 Reset ( XRS) Timing Requirements

MIN

MAX

UNIT

th(boot-mode)

Hold time for boot-mode pins

1.5

tw(RSL2)

Pulse duration, XRS low on

warm reset

All cases

3.2

µs

Low-power modes used in

application and SYSCLKDIV > 16

3.2 * (SYSCLKDIV/16)

8.9.2.2.2 Reset ( XRS) Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER

MIN

TYP

MAX

UNIT

tw(RSL1)

Pulse duration, XRS driven low by device after supplies are

stable

100

µs

tw(WDRS)

Pulse duration, reset pulse generated by watchdog

512tc(OSCCLK)

cycles

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SPRS880O – DECEMBER 2013 – REVISED FEBRUARY 2021

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