ADF4401ABCEZ datasheet(6/39 Pages) AD

6 / 39 page

ADF4401A

Data Sheet

Rev. 0 | Page 6 of 39

TIMING CHARACTERISTICS

See Figure 2, Figure 3, and Figure 4.

Table 2. SPI Timing

Parameter

Min

Typ

Max

Unit

Description

fSCLK

MHz

SCLK frequency

tSCLK

SCLK period

tHIGH

SCLK pulse width high

tLOW

SCLK pulse width low

tDS

SDIO setup time

tDH

SDIO hold time

tACCESS

SCLK falling edge to SDIO valid propagation delay

CS rising edge to SDIO high-z

CS falling edge to SCLK rising edge setup time

SCLK rising edge to CS rising edge hold time

Timing Diagrams

SCLK

SDIO

R/W

D7 D61

D1 D0N

DATA TRANSFER CYCLE

INSTRUCTION CYCLE

A14 A13

SCLK

SDIO

R/W

D61

D0N

DATA TRANSFER CYCLE

INSTRUCTION CYCLE

A14

Figure 2. SPI Timing, MSB First (Upper) and LSB First (Lower)

A14

SCLK

SDIO

tSCLK

tLOW

tHIGH

tDS

tDH

R/W

A13

Figure 3. SPI Write Operation Timing

A14

SCLK

SDIO

tSCLK

tLOW

tHIGH

tDS

tDH

R/W

tACCESS

Figure 4. SPI Read Operation Timing

A14

R/W

A13 A12 A11 A10

DON’T

CARE

DON’T

CARE

DON’T

CARE

DON’T

CARE

SCLK

SDIO

16-BIT INSTRUCTION HEADER

Figure 5. 3-Wire, MSB First, Descending Data, Streaming

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