ADF4401ABCEZ datasheet(30/39 Pages) AD

30 / 39 page

ADF4401A

Data Sheet

Rev. 0 | Page 30 of 39

Address: 0x28, Default: 0x03, Name: REG0028

Los s of Lock Enable.

Lock Detector Count.

[7:3] RESERVED

[0] LOL_EN (R/W)

[2:1] LD_COUNT (R/W)

Table 28. Bit Descriptions for REG0028

Bit(s)

Bit Name

Description

Default

Access

[7:3]

RESERVED

Reserved.

0x0

[2:1]

LD_COUNT

Lock Detector Count. Initial value of the lock detector. This field sets the number of counts

of PFD within lock window before asserting digital lock detect high.

0x1

R/W

0: 1024 cycles.

1: 2048 cycles.

10: 4096 cycles.

11: 8192 cycles.

LOL_EN

Loss of Lock Enable. When loss of lock is enabled, if the digital lock detect is asserted, and

the reference signal is removed, digital lock detect goes low. It is recommended to set to 1

to enable loss of lock.

0x1

R/W

0: disabled.

1: loss of lock enabled.

Address: 0x2B, Default: 0x01, Name: REG002B

Σ-ΔEnable.

Res erved.

Enable Auxiliary SDM.

Mas k

Σ-ΔReset when REG0010

is updated.

[7:6] RESERVED

[0] SD_EN_FRAC0 (R/W)

[5] LSB_P1 (R/W)

[1] RESERVED

[4] VAR_MOD_EN (R/W)

[2] SD_LOAD_ENB (R/W)

[3] RESERVED

Table 29. Bit Descriptions for REG002B

Bit(s)

Bit Name

Description

Default

Access

[7:6]

RESERVED

Reserved.

0x0

LSB_P1

Reserved.

0x0

R/W

VAR_MOD_EN

Enable Auxiliary SDM. Set to 0 for normal operation.

0x0

R/W

RESERVED

Reserved.

0x0

SD_LOAD_ENB

Mask Σ-Δ Reset when REG0010 is updated.

0x0

R/W

RESERVED

Reserved.

0x0

SD_EN_FRAC0

Σ-Δ Enable. Set to 1 when in INT mode (when FRAC1 = FRAC2 = 0), and set to 0 when in

FRAC mode.

0x1

R/W

0: Σ-Δ enabled (for fractional mode).

1: Σ-Δ disabled (for integer mode).

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