ADAQ23875

Data Sheet

Rev. 0 | Page 8 of 23

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

9

10

A

GND

IN1−

IN1+

GND

GND

GND

GND

VIO

GND

CNV+

B

PDB_AMP

IN1−

IN1+

GND

GND

GND

GND

TWOLANES

GND

CNV−

C

GND

VS+

GND

VS+

VS−

GND

GND

GND

GND

GND

D

GND

GND

GND

GND

GND

VCMO

GND

GND

GND

CLK+

E

GND

GND

GND

VS+

GND

GND

GND

GND

GND

CLK−

F

NC

NC

GND

GND

GND

GND

GND

GND

GND

GND

G

GND

GND

GND

GND

GND

GND

GND

GND

GND

DCO+

H

VS+

GND

GND

GND

GND

GND

GND

GND

GND

DCO−

J

VS−

GND

REFBUF

REFBUF

GND

GND

GND

GND

GND

DA+

K

GND

GND

REFIN

GND

PDB_ADC

VDD

TESTPAT

DB−

DB+

DA−

Figure 5. 100-Ball CSP_BGA Pin Configuration, Top View

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Type1

Description

A1, A4 to A7, A9, B4 to B7, B9,

C1, C3, C6 to C10, D1 to D5,

D7 to D9, E1 to E3, E5 to E8,

E9, F3 to F10, G1 to G9, H2 to

H9, J2, J5 to J9, K1, K2, K4

GND

P

Power Supply Ground.

A2, B2

IN1−

AI

Negative Input of the FDA Connected to a 550 Ω Resistor.

A3, B3

IN1+

AI

Positive Input of the FDA Connected to a 550 Ω Resistor.

A8

VIO

P

2.5 V Analog and Output Power Supply. The range of VIO is 2.375 V to 2.625 V. The low

dropout (LDO) regulator output generating the VIO supply of the μModule must be

bypassed with an at least 2.2 μF (0402, X5R) ceramic capacitor to GND.

A10

CNV+

DI

Conversion Start LVDS Input. A rising edge on CNV+ puts the internal sample and

hold in hold mode and starts a conversion cycle. CNV+ can also be driven with a

2.5 V CMOS signal if CNV− is connected to GND.