ADA4355ABCZ datasheet(38/45 Pages) AD

38 / 45 page

ADA4355

Data Sheet

Rev. A | Page 38 of 45

MEMORY MAP

OVERVIEW

The memory map register table (see Table 17) describes the

ADA4355 registers. These registers configure and control the

ADC only.

The memory map is divided into three sections: the chip

configuration registers, the device index register, and the global

ADC function registers, including setup and control.

Each register has eight bit locations. The column with the Bit 7

(MSB) heading contains the most significant bit of the default

hexadecimal value given. For example, Register 0x05, the device

index register, has a hexadecimal default value of 0x33, which

means that in Register 0x05, Bits[7:6] = 00, Bits[5:4] = 11,

Bits[3:2] = 00, and Bits [1:0] = 11 (in binary).

For more information on this SPI port function, see the AN-877

Application Note, Interfacing to High Speed ADCs via SPI.

This application note documents the functions controlled by

Open Locations

In the Table 17, the register bit open locations are reserved to

the ADA4355. These bits must be set to 0 at all times.

Default Values

The default values are available in Table 17.

After power-on, all registers have loaded their default values.

To soft reset the ADA4355, use Register 0x00. All registers,

except the read only register (Register 0x02), are loaded with

default values.

Logic Levels

An explanation of logic level terminology follows:

•

“Bit is set” is synonymous with “bit is set to Logic 1” or

“writing Logic 1 for the bit.”

•

“Clear a bit” is synonymous with “bit is set to Logic 0” or

“writing Logic 0 for the bit.”

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