AD9361S-CSL

Commercial Space Product

Rev. 0 | Page 8 of 33

Parameter1

Symbol

Min

Typ

Max

Unit

Test Conditions/

Comments

DIGITAL DATA TIMING (LVDS)

DATA_CLK_x Clock Period

4.069

ns

245.76 MHz

DATA_CLK_x and FB_CLK_x Pulse

Width

ns

TX Data

TX_FRAME_x and

TX_Dx_x

Setup to FB_CLK_x

1

ns

Hold to FB_CLK_x

0

ns

DATA_CLK_x to Data Bus Output

Delay

0.25

1.25

ns

DATA_CLK_x to RX_FRAME_x Delay

0.25

1.25

ns

Pulse Width

ENABLE

ns

TXNRX

ns

FDD independent ESM

mode

TXNRX Setup to ENABLE

0

ns

TDD ESM mode

Bus Turnaround Time

Before RX

ns

After RX

ns

Capacitive Load

3

pF

Capacitive Input

3

pF

SUPPLY CHARACTERISTICS

1.3 V Main Supply Voltage

1.267

1.3

1.33

V

VDD_INTERFACE Supply

Nominal Settings

CMOS

1.14

2.625

V

LVDS

1.71

2.625

V

VDD_INTERFACE Tolerance

−5

+5

%

Tolerance is applicable

to any voltage setting

VDD_GPO Supply Nominal

Setting

1.3

3.3

V

When unused, must be

set to 1.3 V

VDD_GPO Tolerance

−5

+5

%

Tolerance is applicable

to any voltage setting

Current Consumption

180

μA

Sum of all input

currents

VDD_GPO

50

μA

No load

1

When referencing a single function of a multifunction pin in the parameters, only the portion of the pin name that is relevant to the specification is listed. For full pin

names of multifunction pins, refer to the Pin Configuration and Function Descriptions section.