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PIC24FJ128GL303 bảng dữ liệu(PDF) 33 Page - Microchip Technology |
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PIC24FJ128GL303 bảng dữ liệu(HTML) 33 Page - Microchip Technology |
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33 / 424 page  2019-2020 Microchip Technology Inc. DS30010198B-page 33 PIC24FJ128GL306 FAMILY 4.0 MEMORY ORGANIZATION As Harvard architecture devices, PIC24F micro- controllers feature separate program and data memory spaces and buses. This architecture also allows direct access of program memory from the Data Space (DS) during code execution. 4.1 Program Memory Space The program address memory space of the PIC24FJ128GL306 family devices is 4M instructions. The space is addressable by a 24-bit value derived from either the 23-bit Program Counter (PC) during pro- gram execution, or from table operation or Data Space remapping, as described in Section 4.3 “Interfacing Program and Data Memory Spaces”. User access to the program memory space is restricted to the lower half of the address range (000000h to 7FFFFFh). The exception is the use of TBLRD/TBLWT operations, which use TBLPAG[7] to permit access to the Configuration bits and customer OTP sections of the configuration memory space. The memory map for the PIC24FJ128GL306 family of devices is shown in Figure 4-1. Note: This data sheet summarizes the features of the PIC24FJ128GL306 family of devices. It is not intended to be a comprehensive ref- erence source. For more information, refer to “PIC24F Flash Program Memory” (www.microchip.com/DS30009715) in the “dsPIC33/PIC24 Family Reference Manual”. The information in this data sheet supersedes the information in the FRM. |
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