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VSC8221HH bảng dữ liệu(PDF) 89 Page - Microsemi Corporation |
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VSC8221HH bảng dữ liệu(HTML) 89 Page - Microsemi Corporation |
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89 / 138 page ![]() VSC8221 Data Sheet VMDS-10106 Revision 4.1 December 2006 89 of 106 106 25.15 – interrupt Pin Enable When bit 25.15 is set to “1”, the hardware interrupt is enabled, meaning that the state of the external interrupt pin (MDiNT) can be influenced by the state of the interrupt Status bit (26.15). When bit 25.15 is set to “0”, the interrupt status bits (Register 26) continue to be set in response to interrupts, but the interrupt hardware pin MDiNT on the VSC8221 will not be influenced by this particular PHY. 25.14 – Reserved 25.13 – Link State-Change interrupt Mask When bit 25.13 is set to “1”, the Link State-Change / Energy Detect interrupt is enabled. 25.12 – Reserved 25.11 – Auto-Negotiation Error interrupt Mask When bit 25.11 is set to “1”, the Auto-Negotiation Error interrupt is enabled. 25.10 – Auto-Negotiation-Done / interlock Done interrupt Mask When bit 25.10 is set to “1”, the Auto-Negotiation-Done interrupt is enabled. 25.9 – inline Powered Device Detected interrupt Mask When bit 25.9 is set to “1”, the inline Powered Device Detected interrupt is enabled. 25.8 – Symbol Error interrupt Mask When bit 25.8 is set to “1”, the Symbol Error interrupt is enabled. 25.7 – Descrambler Lock-Lost interrupt Mask When bit 25.7 is set to “1”, the Descrambler Lock-Lost interrupt is enabled. 25.6 – TX FiFO interrupt Mask When bit 25.6 is set to “1”, the TX FiFO interrupt is enabled. 6 TX FiFO interrupt Mask R/W 1 = Enable TX FiFO interrupt 0 = Disable TX FiFO interrupt 0 S 5 RX FiFO interrupt Mask R/W 1 = Enable RX FiFO interrupt 0 = Disable RX FiFO interrupt 0 S 4 Reserved RO 0 3 False Carrier interrupt Mask R/W 1 = Enable False Carrier interrupt 0 = Disable False Carrier interrupt 0 S 2 Cable impairment Detect interrupt Mask R/W 1 = Enable Cable impairment Detect interrupt 0 = Disable Cable impairment Detect interrupt 0 S 1 MASTER/SLAVE Resolution Error interrupt Mask R/W 1 = Enable MASTER/SLAVE interrupt 0 = Disable MASTER/SLAVE interrupt 0 S 0 RXER interrupt Enable R/W 1 = Enable RX_ER interrupt 0 = Disable RX_ER interrupt 0 S Register 25 (19h) – interrupt Mask Register Bit Name Access States Reset Value Sticky |
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