ATM90E32AS-AU-R datasheet(40/84 Pages) ATMEL

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M90E32AS [Datasheet]

Atmel-46003B-SE-M90E32AS-Datasheet_02122015

5.2.2

IRQ AND WARNOUT SIGNAL GENERATION

The interrupt generation scheme is consistent for all the interrupt sources. For any interrupt source, there is an interrupt

status register and an interrupt enable register. Interrupt status register latches the interrupt event and is always available

for polling. If the interrupt enable register is set, that interrupt can go to IRQ pin to notify the processor.

The interrupt status register is write-1-to-clear. It captures the interrupt event which is usually an internal state change. The

(real time) internal state for that event is also available for read at any time.

The following diagram illustrates how the status bits, enable bits and IRQ/ WarnOut pins work together.

Figure-20 IRQ and WarnOut Generation

There are two interrupt output pins: IRQ0 and IRQ1.

The IRQ 0 is associated with interrupt sources defined in EMMState0 register.

The IRQ 1 is associated with interrupt sources defined in EMMState1 register.

If configured, IRQ 1 state can be ORed together with IRQ0 state and output to IRQ0, in that case MCU need only process

one IRQ pin. It is up to system designer to trade off between conveniences of locating interrupt source and saving GPIO

pins.

The Warn pin will be asserted when there is a configuration register CRC check error. The Warn signal can be merged to

IRQ0 if configured.

IRQ0/1

WarnOut

State Reg

Change

event gen

Int Status

Reg

AND

Int En Reg

State Reg

Change

event gen

Int Status

Reg

AND

Int En Reg

State Reg

Change

event gen

Int Status

Reg

AND

Int En Reg

Status Reg

Change

event gen

Int Status

Reg

AND

Int En Reg

State 1

State 2

State 3

Status 4

Internal Err

CfgCRC Err

AND

WarnIrqEn

Reg

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