F4481 datasheet(7/45 Pages) RENESAS

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F4481 Datasheet

December 15, 2020

Number

Name

Description

CLK

Serial clock input. 1.8 V and 3.3 V logic compatible.

DATA

Data write for the 3-wire serial interface. 1.8V and 3.3V logic compatible.

VCC_DIG

Digital power supply. Must place the bypass capacitor as close to the pin as possible.

RFOUT_B

RF output B internally matched to 50Ω. Must use external DC block.

STBY_B

Standby channel B. With Logic LOW applied to this pin (or if the pin is left unconnected), channel B enters STBY

mode and is powered off. With Logic HIGH applied to this pin, channel B is powered on and is fully operational.

RFOUT_A

RF output A internally matched to 50Ω. Must use external DC block.

RDSET_2

Connect external resistor to GND to optimize amplifier performance. Refer to Table 12, Bill of Materials (BOM).

RSET_2

Connect external resistor to GND to optimize amplifier performance. Refer to Table 12, Bill of Materials (BOM).

STBY_A

Standby channel A. With Logic LOW applied to this pin (or if the pin is left unconnected), channel A enters STBY

mode and is powered off. With Logic HIGH applied to this pin, channel A is powered on and is fully operational.

RDSET_1

Connect external resistor to GND to optimize amplifier performance. Refer to Table 12, Bill of Materials (BOM).

RSET_1

Connect external resistor to GND to optimize amplifier performance. Refer to Table 12, Bill of Materials (BOM).

– EPAD

Exposed paddle. Internally connected to ground. Solder this exposed paddle to a printed circuit board (PCB) pad

that uses multiple ground vias to provide heat transfer out of the device into the PCB ground planes. These

multiple ground vias are also required to achieve the specified RF performance.

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