F4481 Datasheet

© 2020 Renesas Electronics Corporation

36

December 15, 2020

Table 10. SPI Timing Diagram Values for the Serial Mode

Parameter

Symbol

Test Condition

Minimum

Typical

Maximum

Units

CLK Frequency

50

MHz

CLK High Duration Time

20

ns

CLK Low Duration Time

20

ns

DATA to CLK Setup Time

10

ns

40

ns

CLK to DATA Hold Time

10

ns

Final CLK Rising Edge to CSb Rising

Edge

10

ns

CSb to CLK Setup Time

10

ns

CSb Trigger Pulse Width

10

ns

10

ns

Standby Mode Programming

Each channel of the F4481 can be placed into a standby mode via the dedicated Channel STBY pins (STBY_A, STBY_B, STBY_C, STBY_D);

for details, see the truth table shown in Table 11. Note that when a channel is disabled, the serial register for that channel will hold the last

enabled DSA state.

Table 11. STBY Logic Truth Table

Channel

STBY_X Pin Logic

Channel Power State

A

0

Channel A Standby (SPI still active)

1

Channel A Power On

B

0

Channel B Standby (SPI still active)

1

Channel B Power On

C

0

Channel C Standby (SPI still active)

1

Channel C Power On

D

0

Channel D Standby (SPI still active)

1

Channel D Power On